VHDL Code for Round Robin Arbiter with Fixed Time Slices

S.No.	Name	Direction	Width	Remark
1	Rst	Input	1	Reset signal
2	Clk	Input	1	Clock signal
3	Req	Input	4	Request for user1 ,user2,user3,user4
4	Gnt	Output	4	four grant signal to the Users

Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system. As the term is generally used, time slices are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. Find out Round Robin Arbiter with variable time slice here.

library ieee;
use ieee.std_logic_1164.all;

entity round_robin is

  port (
    req : in  std_logic_vector(3 downto 0);  -- Request signal
    gnt : buffer std_logic_vector(3 downto 0);  -- grant signal
    clk : in  std_logic;                     -- system clock
    rst : in  std_logic);                    -- async reset

end round_robin;


architecture arch of round_robin is

type state is (s_idle,s0,s1,s2,s3);       -- State declaration
signal present_state,next_state : state;  -- State container
begin  -- arch

  -- purpose: fixing the priority and grant signal assignment
  -- type   : combinational
  -- inputs : req
  -- outputs: gnt
  priority: process (present_state,req)
  begin  -- process priority

    case present_state is

      when s_idle =>
        if(req(0)='1')then
          gnt<="0001";
          next_state<=s0;
        elsif req(1)='1' then
          gnt<="0010";
          next_state<=s1;
        elsif req(2)='1' then
          gnt<="0100";
          next_state<=s2;
        elsif req(3)='1' then
          gnt<="1000";
          next_state<=s3;
        else
            gnt<="0000";
            next_state<=s_idle;
        end if;

      when s0 =>
        if(req(1)='1')then
          gnt<="0010";
          next_state<=s1;
        elsif req(2)='1' then
          gnt<="0100";
          next_state<=s2;
        elsif req(3)='1' then
          gnt<="1000";
          next_state<=s3;
        elsif req(0)='1' then
          gnt<="0001";
          next_state<=s0;
        else
          gnt<="0000";
          next_state<=s_idle;
        end if;

        when s1 =>
        if(req(2)='1')then
          gnt<="0100";
          next_state<=s2;
        elsif req(3)='1' then
          gnt<="1000";
          next_state<=s3;
        elsif req(0)='1' then
          gnt<="0001";
          next_state<=s0;
        elsif req(1)='1' then
          gnt<="0010";
          next_state<=s1;
        else
          gnt<="0000";
          next_state<=s_idle;
        end if;

        when s2 =>
        if(req(3)='1')then
          gnt<="1000";
          next_state<=s3;
        elsif req(0)='1' then
          gnt<="0001";
          next_state<=s0;
        elsif req(1)='1' then
          gnt<="0010";
          next_state<=s1;
        elsif req(2)='1' then
          gnt<="0100";
          next_state<=s2;
        else
          gnt<="0000";
          next_state<=s_idle;
        end if;

        when s3 =>
        if(req(0)='1')then
          gnt<="0001";
          next_state<=s0;
        elsif req(1)='1' then
          gnt<="0010";
          next_state<=s1;
        elsif req(2)='1' then
          gnt<="0100";
          next_state<=s2;
        elsif req(3)='1' then
          gnt<="1000";
          next_state<=s3;
        else
            gnt<="0000";
            next_state<=s_idle;
        end if;
         
    end case;
  end process priority;


  -- purpose: State Assignment
  -- type   : sequential
  -- inputs : clk, rst, present_state
  -- outputs: next_state


  State_assignment: process (clk, rst)
  begin  -- process State_assignment
    if rst = '1' then                   -- asynchronous reset (active high)
      present_state<=s_idle;
    elsif clk'event and clk = '1' then  -- rising clock edge
      present_state<=next_state;
    end if;
  end process State_assignment;


-- purpose: Assertion_assignment
  -- type   : combinational
  -- inputs : gnt
  -- outputs:
  Assertion_assignment: process (gnt)
  begin  -- process Assertion_assignment
    if(gnt="0001")then
      assert false report "Request 0 is granted" severity note;
 
    elsif gnt="0010" then
      assert false report "Request 1 is granted" severity note;
 
    elsif gnt="0100" then
      assert false report "Request 2 is granted" severity note;
 
    elsif gnt="1000" then
      assert false report "Request 3 is granted" severity note;
    end if;
  end process Assertion_assignment;
end arch;