A Brief Overview Of Data Type in VHDL.

VHDL is strongly typed language and it supports a variety of Data Types and Operators. Users can also define their own data types and operators in user defined packages. There are three basic classes to define data objects in VHDL language.

• Signal : It represents interconnections that connect components and parts.
• Variable : It is used for local storage within process.
• Constant : It is used to declare a fixed value.

The data object can be a scalar or an array (one dimensional as well as multi dimensional).

Get Knowledge of Operators in VHDL with Examples

VHDL has wide range of Operators, which can be grouped into following

• Logical Operators
• Relational Operators
• Shift Operators.
• Miscellaneous Operators

Get Knowledge of Delay Types in VHDL

In VHDL, delays are specified only in signal assignment not in variable assignment. Delays are not synthesizable. There are two types of delay in VHDL Language.

1. Transport Delay
2. Inertial Delay

• Transport Delay : It is the delay model just delay the signal or change the value of the signal by the time specified in the after clause. It is the characteristic of the hardware elements that exhibits infinite frequency response. Any pulse is transmitted no matter how small it is.

VHDL Programming Code Structure

VHDL stands for Very High speed integrated circuits Hardware Description Language. It was funded by the US Department of Defense in the 70’s and 80’s. It was established as IEEE standard IEEE 1076 in 1987. It was later updated on 1993, 2002 and 2008. Today VHDL is widely used across the industry for design description, simulation and synthesis purpose.

Here General Structure of VHDL Program is given below

·         Library Declaration

·         Package Declaration

·         User Defined Library Declaration*

·         User Defined Package Declaration*

·         Entity Declaration

o   Generic Declaration

o   Port Declaration

·         Architecture Declaration

·         Configuration Declaration

Shift Operators in VHDL

Shift operators are playing very important role in VHDL language. It is very usefull to shift or rotate digits of binary numbers.

There are total six shifting operators in VHDL language.

•  sll

• It means Logical Shift Left.

• It shifts the elements in the array by n places to left and fill vacanted positions with "0".

• Ex

• "1000_1010" sll 3 will give "0101_0000".

• "1000_1010" sll -2 will give "0010_0010".