VHDL Code for Asynchronous Reset D-FlipFlop

library ieee;
use ieee.std_logic_1164.all;

  entity dff_async_reset is
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          enb     :in  std_logic;  -- enable pin
          load    :in  std_logic   -- load the input
      );
  end entity;

  architecture beh of dff_async_reset is

  begin
      process (clk,reset_a,enb,load)
           begin
         
          if (reset_a = '1') then
              q <= '0';
          elsif(rising_edge(clk) and enb ='1') then
              if(load = '1') then
                q <= '1';
              else
                q<= data;
              end if;          
          end if;
    end process;
end architecture;