Easy UVM (Universal Verification Methodology) Tutorial

UVM stands for Universal Verification Methodology. It is standard methodology to verify Integrated Circuits. UVM is derived from OVM, Open Verification Methodology. UVM is developed by Accellera with the support of Aldec, Cadence, Mentor Graphics and Synopsys. UVM is based on System Verilog language. With the help of UVM, engineers are able to create an efficient verification environment. It is portable from one project to another. Due to portability, engineers can reuse testbench from previous projects and modify different components as per their need. UVM easy tutorial is shown below. It is available on YouTube. It is developed by John Aynsley from Doulos. There are twenty videos. After watching this tutorial, overall picture of UVM will be cleared. 

Design a Constant Divider using VHDL Coding.

Constant Divider circuit accepts an input of 8 bit wide and divides it by constant value 53. The divider circuit will generate two output values as remainder and quotient. As we know that the division operator is not synthesizable, so division is done by repetitive subtraction method. As an example of input is 108, the remainder is 2 and quotient is 2 while if input is 20, remainder is 20 and quotient is 0. In this design Inp is input with 8 bit long, Remi and Quo are two output signals with 6-bit and 3-bit long respectively. Here bit lengths of Remi and Quo are decided as per getting maximum value. Divider is constant which is 8 bit long and value is "00110101". Binary value of 53 is "00110101".

Design 4-bit Linear Feedback Shift Register (LFSR) using VHDL Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. It is used for State Encoding. It is also used to generate random numbers. Find out Verilog code here.

Design 8 bit Ripple Carry Adder using VHDL Coding and Verify using Test Bench

Given below code will generate 8 bit output as sum and 1 bit carry as cout.  it also takes two 8 bit inputs as a and b, and one input carry as cin. This code is implemented in VHDL by structural style. Predefined full adder code is mapped into this ripple carry adder. Full Adder code can be found here. Carry is generated by adding each bit of two inputs and propagated to next bit of inputs. If carry is generated by adding seventh bits and previous carry, then cout bit goes high.

Design Gray Counter using VHDL Coding and Verify with Test Bench

Given below code is about Gray Counter in VHDL. In a gray code only one bit changes at a one time. This design code has two inputs clock and reset signals and one four bit output that will generate gray code. In the first if rst signal is high then output will be zero and as soon as rst will go low, on the rising edge of clk, design will generate four bit gray code and continue to generate at every rising edge of clk signal. This design code can be upgraded and put binary numbers as a input and this design will work as binary to gray code converter. Find out Verilog Code of Gray Counter here.

Test Bench for 8-bit Barrel Shifter in VHDL

Find out Design Code Here.

library ieee;
use ieee.std_logic_1164.all;

entity barrel_shifter_tst is

end barrel_shifter_tst;


architecture beh of barrel_shifter_tst is

    component barrel_shifter

    port (
    d_in        : in  std_logic_vector(7 downto 0);   -- input vector
    d_out       : out std_logic_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  std_logic;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  std_logic_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  std_logic;                      -- clock signal
    rst_a       : in  std_logic);                     -- reset signal

 
  end component;
 
signal rst_a_s : std_logic;
signal shift_lt_rt_s: std_logic;
signal shift_by_s : std_logic_vector(2 downto 0);
signal d_out_s,d_in_s : std_logic_vector(7 downto 0);
signal clk_s : std_logic := '1';          -- clk signal

begin  -- arch

  u1 : barrel_shifter port map (
  rst_a      => rst_a_s,
  clk        => clk_s,
  shift_lt_rt   => shift_lt_rt_s,
  d_in       => d_in_s,
  shift_by   => shift_by_s,
  d_out     => d_out_s);


  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 50 ns;

   clk_s <= '0';
    wait for 50 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "001";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "010";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "001";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "010";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "101";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "111";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "011";
    d_in_s <= "11001101";
    wait for 100 ns;
  end process tst;

end beh;

Test Bench for Parity Generator in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity parity_generator_tst is

end parity_generator_tst;

architecture beh of parity_generator_tst is

component parity_generator
  port(clk,d_in, rst_a,valid_in : in std_logic;
       valid_out,parity_out: out std_logic;
        data_o : out std_logic_vector(7 downto 0));
end component;

signal clk_s,rst_a_s,valid_in_s,d_in_s,parity_out_s,valid_out_s : std_logic;
signal data_o_s : std_logic_vector(7 downto 0);

begin  -- beh

  u1 : parity_generator port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    valid_in  => valid_in_s,
    d_in    => d_in_s,
    valid_out => valid_out_s,
    parity_out => parity_out_s,
    data_o     => data_o_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 50 ns;

    clk_s <= '0';
    wait for 50 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '0';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '0';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '1';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

  end process tst;

end beh;

Test Bench for 4-bit Up-Down Counter with Pre-Load in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity up_counter_sync_preload_tst is

end up_counter_sync_preload_tst;

architecture beh of up_counter_sync_preload_tst is

component up_counter_sync_preload
  port(clk, rst_a,load : in std_logic;
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0));
end component;

signal clk_s,rst_a_s,load_s : std_logic;
signal ip_s,q_s : std_logic_vector(3 downto 0);

begin  -- beh

  u1 : up_counter_sync_preload port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    load  => load_s,
    ip    => ip_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;

    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '1';
    ip_s <= "1101";
    wait for 100 ns;

    rst_a_s <= '0';
    load_s <= '0';
    ip_s <= "1100";
    wait for 100 ns;
  end process tst;

end beh;

Test Bench for 4-bit Up-Down Counter in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity up_down_counter_tst is

end up_down_counter_tst;

architecture beh of up_down_counter_tst is

component up_down_counter
  port(clk, rst_a,mode : in std_logic;
      q : out std_logic_vector(3 downto 0));
end component;

signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);

begin  -- beh

  u1 : up_down_counter port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    mode  => mode_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;

    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
   wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
  end process tst;

end beh;

Test Bench for Asynchronous Reset D-FlipFlop in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity dff_async_reset_tst is
 
end dff_async_reset_tst;

architecture beh of dff_async_reset_tst is
component dff_async_reset
  port (
    data, load, reset_a, clk, enb : in  std_logic;   -- inputs
    q                             : out std_logic);  -- output
end component;
  signal data_s,load_s,reset_a_s,clk_s,enb_s : std_logic := '0';
  signal q_s : std_logic;
begin  -- beh

  u1 : dff_async_reset port map (
    data    => data_s,
    load    => load_s,
    reset_a => reset_a_s,
    clk     => clk_s,
    enb     => enb_s,
    q       => q_s);

  tst_p: process
  begin  -- process tst_p
    clk_s <= '1';
    wait for 55 ns;
    clk_s <= '0';
    wait for 55 ns;
  end process tst_p;

 dff: process
 begin  -- process dff
   reset_a_s <= '1';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '1';
   data_s <= '0';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '1';
   wait for 100 ns;
      reset_a_s <= '0';
   enb_s <= '1';
   load_s <= '0';
   data_s <= '0';
   wait for 100 ns;
 
 end process dff;
end beh;

Test Bench For 4-Bit Magnitude Comparator in VHDL

Find out VHDL code of Magnitude Comparator here.

library ieee;
use ieee.std_logic_1164.all;

entity mag_comp_4b_tst is
  
end mag_comp_4b_tst;

architecture beh of mag_comp_4b_tst is

component mag_comp_4b
  port (
    a, b : in  std_logic_vector(3 downto 0);                     -- inputs
    ag,bg,eq    : out std_logic);                    -- output
end component;
signal a_s,b_s : std_logic_vector(3 downto 0);
signal ag_s,bg_s,eq_s : std_logic;
  
begin  -- beh

  u1 : mag_comp_4b port map (
    a => a_s,
    b => b_s,
    ag => ag_s,
    eq => eq_s,
    bg => bg_s);
  tst_p:process
    begin
      a_s<="1111";
      b_s<="0000";
      wait for 100 ns;
       a_s<="1010";
      b_s<="1100";
      wait for 100 ns;
       a_s<="1001";
      b_s<="0011";
      wait for 100 ns;
       a_s<="1000";
      b_s<="1000";
      wait for 100 ns;

    end process;

end beh;

Simulated waveform of Magnitude Comparator is given below. This code is simulated using Xilinx Vivado.

Simulation Waveform of Magnitude Comparator

Test Bench for Half Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity half_adder_tst is
  
end half_adder_tst;
 architecture beh of half_adder_tst is
   component half_adder
       port (
    ip1,ip2: in  std_logic;   -- inputs
    sum,ca: out std_logic);  -- outputs

end component;
    signal ip1_s,ip2_s : std_logic;  -- signals
    signal sum_s,ca_s : std_logic;  -- output signals
 begin  -- beh

u1 : half_adder port map (
  ip1 => ip1_s,
   ip2 => ip2_s,
   sum => sum_s,
  ca => ca_s);

tst_p: process
   begin
      ip1_s<='0';
       ip2_s<='0';
       wait for 100 ns;
       ip1_s<='0';
       ip2_s<='1';
       wait for 100 ns;
       ip1_s<='1';
       ip2_s<='0';
       wait for 100 ns;
       ip1_s<='1';
       ip2_s<='1';
       wait for 100 ns;
    end process;
       
 end beh;

Test Bench for 4-Bit Full Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_4b_tst is
 
end full_adder_4b_tst;
 architecture beh of full_adder_4b_tst is
   component full_adder_4b
       port (
    a,b: in  std_logic_vector(3 downto 0);   -- inputs
     c :inout std_logic_vector(4 downto 1);  --carry out
    s: out std_logic_vector(3 downto 0));  -- outputs

end component;
    signal a_s,b_s : std_logic_vector(3 downto 0);  -- signals
    signal s_s : std_logic_vector(3 downto 0);  -- output signals
    signal c_s : std_logic_vector(4 downto 1);
 begin  -- beh

u1 : full_adder_4b port map (
  a => a_s,
   b => b_s,
   c => c_s,
   s => s_s);

tst_p: process
   begin
      a_s<="0000";
       b_s<="0101";
       wait for 100 ns;
       a_s<="1100";
       b_s<="0100";
       wait for 100 ns;
       a_s<="1111";
       b_s<="0000";
       wait for 100 ns;
       a_s<="0010";
       b_s<="1101";
       wait for 100 ns;
      end process;
  end beh;

Test Bench for 1-Bit Full-Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_con_tst is
  
end full_adder_con_tst;
 architecture beh of full_adder_con_tst is
   component full_adder_con
       port (
    a,b,c: in  std_logic;   -- inputs
    sum,ca: out std_logic);  -- outputs

end component;
    signal a_s,b_s,c_s : std_logic;  -- signals
    signal sum_s,ca_s : std_logic;  -- output signals
 begin  -- beh

u1 : full_adder_con port map (
  a => a_s,
   b => b_s,
   c => c_s,
   sum => sum_s,
  ca => ca_s);

tst_p: process
   begin
      a_s<='0';
       b_s<='0';
       c_s<='0';
       wait for 100 ns;
       a_s<='0';
       b_s<='0';
       c_s<='1';
       wait for 100 ns;
       a_s<='0';
       b_s<='1';
       c_s<='0';
       wait for 100 ns;
       a_s<='0';
       b_s<='1';
       c_s<='1';
       wait for 100 ns;
       a_s<='1';
       b_s<='0';
       c_s<='0';
       wait for 100 ns;
       a_s<='1';
       b_s<='0';
       c_s<='1';
       wait for 100 ns;
       a_s<='1';
       b_s<='1';
       c_s<='0';
       wait for 100 ns;
       a_s<='1';
       b_s<='1';
       c_s<='1';
       wait for 100 ns;
    end process;
 end beh;

Test Bench for 4x1 Multiplexer in VHDL

Find out Design code of 4x1 Mux here.

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1_seq_tst is
  
end mux4x1_seq_tst;
 architecture beh of mux4x1_seq_tst is
   component mux4x1_seq
   port (
    ip0 : in  std_logic;   -- input pin
    ip1 : in  std_logic;   -- input pin
    ip2 : in  std_logic;   -- input pin
    ip3 : in  std_logic;   -- input pin
    s : in std_logic_vector(0 to 1);     --select line
    op : out std_logic);  -- output 

end component;
    signal  ip0_s :  std_logic;   -- input signal
   signal  ip1_s :  std_logic;   -- input signal
   signal ip2_s :  std_logic;   -- input signal
   signal ip3_s :  std_logic;   -- input signal
   signal  s_s :  std_logic_vector(0 to 1);     --msb of select line signal
   signal  op_s :  std_logic;  -- output siganl
 begin  -- beh

u1 : mux4x1_seq port map (
  ip0 => ip0_s,
   ip1 => ip1_s,
   ip2 => ip2_s,
   ip3 => ip3_s,
   s => s_s,
  op => op_s);
tst_p: process
   begin
      ip0_s<='1';
       ip1_s<='0';
       ip2_s<='0';
       ip3_s<='0';
       s_s<="00";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='1';
        ip2_s<='0';
        ip3_s<='0';
       s_s<="10";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='0';
        ip2_s<='1';
        ip3_s<='0';
       s_s<="01";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='0';
        ip2_s<='0';
        ip3_s<='1';
       s_s<="11";
       wait for 100 ns;
   end process;

 end beh;

Test Bench for 1x4 DeMultiplexer in VHDL

Find out DeMultiplexer Code here.

library ieee;
use ieee.std_logic_1164.all;

entity dmux1x4_seq_tst is
  
end dmux1x4_seq_tst;
 architecture beh of dmux1x4_seq_tst is
   component dmux1x4_seq
    port (
    s  : in  std_logic_vector(1 downto 0);  -- select lines
    i : in std_logic;                       -- input
   op  : out  std_logic_vector(3 downto 0)  -- outputs
   );

end component;
    signal ip_s : std_logic;  -- signals
    signal op_s : std_logic_vector(3 downto 0);  -- output signals
    signal s_s : std_logic_vector(1 downto 0);  -- select line signals
 begin  -- beh

u1 : dmux1x4_seq port map (
  i => ip_s,
  s => s_s,
  op => op_s);

tst_p: process
   begin
      ip_s<='1';
       s_s<="00";
       wait for 100 ns;
       ip_s<='1';
       s_s<="01";
       wait for 100 ns;
       ip_s<='1';
       s_s<="10";
       wait for 100 ns;
       ip_s<='1';
       s_s<="11";
       wait for 100 ns;
    end process;

 end beh;

Test Bench for 8x3 Encoder in VHDL

Find out VHDL code for 8x3 Encoder here.

library ieee;
use ieee.std_logic_1164.all;

entity enco8x3_seq_tst is
  
end enco8x3_seq_tst;
 architecture beh of enco8x3_seq_tst is
   component enco8x3_seq
       port (
    i: in  std_logic_vector(7 downto 0);   -- inputs
    o: out std_logic_vector(2 downto 0));  -- outputs

end component;
    signal i_s : std_logic_vector(7 downto 0);  -- signals
    signal o_s : std_logic_vector(2 downto 0);  -- output signals
 begin  -- beh

u1 : enco8x3_seq port map (
  i => i_s,
  o => o_s);

tst_p: process
   begin
       i_s<="00000001";
       wait for 100 ns;
       i_s<="00000010";
       wait for 100 ns;
       i_s<="00000100";
       wait for 100 ns;
       i_s<="00001000";
       wait for 100 ns;
       i_s<="00010000";
       wait for 100 ns;
       i_s<="00100000";
       wait for 100 ns;
       i_s<="01000000";
       wait for 100 ns;
       i_s<="10000000";
       wait for 100 ns;
    end process;
 end beh;

Test Bench for 3x8 Decoder in VHDL

Find out VHDL code for 3x8 Decoder here.

library ieee;
use ieee.std_logic_1164.all;

entity deco3x8_seq_tst is

end deco3x8_seq_tst;
 architecture beh of deco3x8_seq_tst is
   component deco3x8_seq
       port (
    ip: in  std_logic_vector(2 downto 0);   -- inputs
    op: out std_logic_vector(7 downto 0));  -- outputs

end component;
    signal ip_s : std_logic_vector(2 downto 0);  -- signals
    signal op_s : std_logic_vector(7 downto 0);  -- output signals
 begin  -- beh

u1 : deco3x8_seq port map (
  ip => ip_s,
  op => op_s);

tst_p: process
   begin
      ip_s<="000";
       wait for 100 ns;
       ip_s<="001";
       wait for 100 ns;
       ip_s<="010";
       wait for 100 ns;
       ip_s<="011";
       wait for 100 ns;
       ip_s<="100";
       wait for 100 ns;
       ip_s<="101";
       wait for 100 ns;
       ip_s<="110";
       wait for 100 ns;
       ip_s<="111";
       wait for 100 ns;
    end process;
 end beh;