Pulse Transfers and Fast-to-Slow Clock Domain Crossing

From the last post, you know how to use a 2-Flop Synchronizer for single control bits, and you know how to use Handshakes and Asynchronous FIFOs for multi-bit data buses.

But there is one specific, highly common scenario that will silently break a standard 2-Flop Synchronizer: passing a single-cycle pulse from a very fast clock domain to a very slow clock domain.

Let's dive into the "Disappearing Pulse" problem and the clever hardware tricks VLSI engineers use to solve it.

The Disappearing Pulse Problem

Imagine you have a high-speed networking chip. A packet arrives, and the 1GHz receiver logic generates a single-cycle packet_received pulse. You need to send this pulse to a 100MHz microcontroller on the same chip so it can log the event.

You route the 1GHz pulse directly into a standard 2-Flop Synchronizer running at 100MHz. You run the simulation, and... nothing happens. The microcontroller never sees the pulse. What went wrong?

It comes down to simple math and timing:

• A single clock cycle at 1GHz is exactly 1 nanosecond long. Your pulse exists for exactly 1ns.

• A 100MHz clock only ticks once every 10 nanoseconds.

If the 1ns pulse fires and disappears between the 10ns ticks of the slow clock, the slow clock's flip-flops will never see it. The data violates the fundamental rule of sampling: the signal must be stable long enough for the destination clock to actually sample it.

Handshakes, FIFOs, and the Magic of Gray Code in Multi-Bit CDC

 In our last post, we tackled the silent silicon killer known as Metastability and explored how the trusty 2-Flop Synchronizer safely passes a single control bit across different clock domains. 

But what happens when you need to send an entire 32-bit data bus from a 1GHz processor to a 400MHz memory controller? 

Spoiler alert: You cannot just slap thirty-two 2-Flop Synchronizers in parallel and call it a day. Today, we are diving into the practical magic of Asynchronous FIFOs and why a mathematical curiosity from the 1940s called Gray Code is the only thing keeping modern microchips from collapsing into chaos.

The Multi-Bit Disaster: Why 2-Flop Synchronizers Fail on Buses

Imagine trying to pass a binary counter value of 3 (011 in binary) changing to 4 (100 in binary) across a clock domain using parallel synchronizers. Notice that three separate bits are changing simultaneously to make that jump.

In the physical world of silicon, perfectly simultaneous events do not exist. Microscopic variations in wire routing, parasitic capacitance, and temperature mean those three bits will arrive at the destination flip-flops at slightly different picoseconds. This is called Bus Skew.

If the destination clock ticks exactly while those bits are transitioning, some flip-flops will capture the old value, some will capture the new value, and some will go metastable. Your destination domain might stitch those bits together and read 7 (111) or 0 (000). This generates a garbage memory address that will instantly crash your system.

To fix this, we have two primary weapons in RTL design: Handshaking and Asynchronous FIFOs.

Understanding Metastability and Clock Domain Crossing (CDC)

If you’ve taken a digital logic class, you know the golden rule: everything happens on the clock edge. Your flip-flops read the input, store the state, and pass it to the next logic gate in perfect synchronization.

But what happens when your design has more than one clock?

In modern ASICs and FPGAs, a single chip might have a 1GHz processor, a 400MHz memory controller, and a 50MHz UART interface. When data needs to move between these independent clock domains—a process known as Clock Domain Crossing (CDC)—the perfect synchronization of the classroom goes out the window, and you enter the dangerous territory of Metastability. 

The Setup and Hold Violation 

To understand metastability, we have to look at the physical physics of a flip-flop. For a flip-flop to reliably capture a 1 or a 0, the data signal must be stable for a specific amount of time before the clock edge (Setup Time) and remain stable for a specific amount of time after the clock edge (Hold Time).

When data crosses from Domain A (e.g., 100MHz) to Domain B (e.g., 33MHz), Domain B's clock has no idea when Domain A's data is changing. It is almost guaranteed that eventually, Domain B's clock will tick exactly at the moment Domain A's data is transitioning between a 0 and a 1.

This violates setup and hold times, causing the flip-flop to go metastable. 

The Ultimate Base Converter: Bridging the Gap Between Humans and Hardware

Base Converter

Decimal (Base 10)

Invalid decimal character

Binary (Base 2)

Invalid binary character (Use 0 or 1)

Octal (Base 8)

Invalid octal character (Use 0-7)

Hexadecimal (Base 16)

Invalid hex character (Use 0-9, A-F)

Rising and Falling Edge Detector using Verilog

 In the real word, there might be many scenario that we need to detect rising edge or falling edge of the signal. If rising/falling edge happens on particular signal, then design can perform certain task. This rising or falling edge can be detected using following code. This code is done in Verilog language. In given below example code, clock clk, input signal sig_a, output rising edge signal ris_a and falling edge signal fal_a are defined. Both ris_a and fal_a are high for one clock cycle when circuit detects rising or falling edge on the sig_a respectively.

Excitation and Characteristic Table of SR Flip Flop

The basic SR Flip-Flop is shown below. The inputs, labeled S and R are used to SET and RESET the device, respectively. The outputs Q and Q’ are complementary. Because the Flip-Flop is unclocked, any change to the inputs will produce a change at the outputs. An invalid state occurs when both inputs are low; thus, the inputs should be kept high except when the Flip-Flop is to be set or cleared. Note that there are other implementations for a latch. Here we are showing a NAND implementation.

Number System in Digital Design

To represent something we require symbols and to represent count we require Numbers. Number System is very important in Digital Technology. The most commonly used number systems are Decimal(Base 10), Binary(Base 2), Hexadecimal(Base 16) and Octal(Base 8). We all are very much familiar with Decimal Number System.

Logic Gates with Truth Table in Digital World

Logic gates are basic building blocks of any digital circuits. Logic gates are electronics device that gives output on the different combinations of digital inputs. Different Logic gates are constructed using different technologies depending on different Logic Family like TTL, CMOS, DTL, ECL etc. Logic Circuits include devices such as multiplexers, registers, memory units, processors, which contains more than 100 millions Logic Gates.

There are total six Logic Gates are available

1. AND Gate.
2. OR Gate.
3. NOT Gate.
4. NAND Gate.
5. NOR Gate.
6. EX-OR Gate.
7. EX-NOR Gate.

Implement Divide by 2, 4, 8 and 16 Counter using Flip-Flop

Counter plays a very important role into chip designing and verification. It is a very essential part of the VLSI Domain. Whenever we want to design or verify our design, most of the time we require slowing down frequencies. We can suppress this frequency using this counter by 2, 4, 8 or 16 times. Here circuit diagram and verilog code are given below.

Setup Time and Hold Time

These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output. 

Setup Time: - It’s a time interval before the Clock signal is triggered, where Data signal should be stable. So, that Data is easily sampled by the Flip-Flop.

Difference between Flip-Flop and Latch

Flip-Flop	Latch
Flip-Flop is Edge sensitive device.	Latch is Level sensitive device.
In Flip-Flop, output will change on rising or falling edge of clock signal.	In Latch, if Enable/Clock signal is high then output will change accordingly input.
So, we can say that Flip-Flop is a Synchronous version of Latch.	So, we can say that Latch is Asynchronous device.
Flip-Flop based design creates less timing problems.	Latch based design creates more timing problems.
In design Flip-Flop takes more area compared to Latch.	In design Latch takes less area compared to Flip-Flop.
In design Flip-Flop consumes more power compare to Latch.	In design Latch consumes less power compare to Flip-Flop.

Implement XOR Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Multiplexer's input to input 'B'. Connect input 'B' to input of NOT gate and output of this NOT gate connect to second input of Multiplexer. Then connect input 'A' to selection line of Multiplexer. So, this Multiplexer will XORing operation of input A, B.

Implement OR Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Mux's input to logic '1' and second to input 'B'. Connect input 'A' to selection line of Mux. So, output will give ORing operation of two inputs A, B.

Implement AND Gate using 2x1 Multiplexer

We have two inputs A, B. Connect one of Mux's input to logic '0' and second to input 'B'. Connect input A to selection line of Mux. So, output of Mux will give anding operation of two inputs A and B.

Implement BUFFER Gate using XOR Gate

Connect one of XOR gate's input to logic '0' and connect second to input 'a'. So XOR gate will give output as input.

Implement NOT Gate using XOR Gate

Connect one of XOR gate's input to logic 1 and connect second input to input 'a'. So output of XOR gate will give inverted output of input.