VHDL Code for Half-Adder

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is

  port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    sum : out std_logic;
    ca  : out std_logic);

end half_adder;

architecture half_adder_beh of half_adder is

begin  -- half_adder_beh

  sum <= ip1 xor ip2;
  ca <= ip1 and ip2;

end half_adder_beh;