Test Bench for 4-bit Up-Down Counter in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity up_down_counter_tst is

end up_down_counter_tst;

architecture beh of up_down_counter_tst is

component up_down_counter
  port(clk, rst_a,mode : in std_logic;
      q : out std_logic_vector(3 downto 0));
end component;

signal clk_s,rst_a_s,mode_s : std_logic;
signal q_s : std_logic_vector(3 downto 0);

begin  -- beh

  u1 : up_down_counter port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    mode  => mode_s,
    q     => q_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 55 ns;

    clk_s <= '0';
    wait for 55 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
   wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    mode_s <= '1';
    wait for 100 ns;
  end process tst;

end beh;