Test Bench for Parity Generator in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity parity_generator_tst is

end parity_generator_tst;

architecture beh of parity_generator_tst is

component parity_generator
  port(clk,d_in, rst_a,valid_in : in std_logic;
       valid_out,parity_out: out std_logic;
        data_o : out std_logic_vector(7 downto 0));
end component;

signal clk_s,rst_a_s,valid_in_s,d_in_s,parity_out_s,valid_out_s : std_logic;
signal data_o_s : std_logic_vector(7 downto 0);

begin  -- beh

  u1 : parity_generator port map (
    clk   => clk_s,
    rst_a => rst_a_s,
    valid_in  => valid_in_s,
    d_in    => d_in_s,
    valid_out => valid_out_s,
    parity_out => parity_out_s,
    data_o     => data_o_s);

  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 50 ns;

    clk_s <= '0';
    wait for 50 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '0';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '0';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '1';
    valid_in_s <= '1';
    d_in_s <= '0';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    valid_in_s <= '1';
    d_in_s <= '1';
    wait for 100 ns;

  end process tst;

end beh;