Test Bench for Half Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity half_adder_tst is
  
end half_adder_tst;
 architecture beh of half_adder_tst is
   component half_adder
       port (
    ip1,ip2: in  std_logic;   -- inputs
    sum,ca: out std_logic);  -- outputs

end component;
    signal ip1_s,ip2_s : std_logic;  -- signals
    signal sum_s,ca_s : std_logic;  -- output signals
 begin  -- beh

u1 : half_adder port map (
  ip1 => ip1_s,
   ip2 => ip2_s,
   sum => sum_s,
  ca => ca_s);

tst_p: process
   begin
      ip1_s<='0';
       ip2_s<='0';
       wait for 100 ns;
       ip1_s<='0';
       ip2_s<='1';
       wait for 100 ns;
       ip1_s<='1';
       ip2_s<='0';
       wait for 100 ns;
       ip1_s<='1';
       ip2_s<='1';
       wait for 100 ns;
    end process;
       
 end beh;