Verilog code to count number of 1's and 0's in 32-bit data input

There are many places where we need to check how many 0's or 1's are present in incoming data. It can be packet inspection or these counting further can be used for different purposes. This Verilog code is designed to efficiently count the occurrences of both '1' and '0' bits within a 32-bit input data. The primary objective of this module is to provide an accurate count of the number of '1's and '0's present in the input data simultaneously. Module takes 32-bit input data with valid bit. There are also clock and reset signals. Module has two output count vlaues, one for number of 1's and another one for number of 0's, and one valid signal. 32-bit input data is fed to the function only on valid_input and function will return number of 1's in the 32-bit data. This value will be subtracted from 32 and it will give us number of 0's present in the data. Both output values are true only when output_valid signal is high.

Rising and Falling Edge Detector using Verilog

 In the real word, there might be many scenario that we need to detect rising edge or falling edge of the signal. If rising/falling edge happens on particular signal, then design can perform certain task. This rising or falling edge can be detected using following code. This code is done in Verilog language. In given below example code, clock clk, input signal sig_a, output rising edge signal ris_a and falling edge signal fal_a are defined. Both ris_a and fal_a are high for one clock cycle when circuit detects rising or falling edge on the sig_a respectively.

Verilog Code for (7,4) Systematic Hamming Encoder

Hamming code is useful in Error Correction in Linear Block Code. This code will encode four bits of data and generate seven bits of code by adding three bits as parity bits. It was introduced by Richard W. Hamming. This algorithm can detect one and two bit error and can correct one bit error. Given below code will generate (7,4) Systematic Hamming Encoder. This encoder will use Least Significant 4 bits as data inputs and Most 3 significant bits as a parity bits.

Get VHDL Code.

Design BCD to 7-Segment Decoder using Verilog Coding

Given below Verilog code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find VHDL Code here.

Common Cathode Seven Segment Display

Design 4 bit Magnitude Comprator using Verilog and Verify with Test Bench

This design accepts two four bit inputs 'a' and 'b' and generates three one bit outputs 'eq', 'gt' and 'lt'. If both inputs are same then 'eq' bit will be high and other two outputs will be low. If 'a' is greater than 'b' then 'gt' will be high and other two outputs will be low. Same way if 'a' is less than 'b' then 'lt' output will go high and other two output will go low.

Verilog and VHDL Code for Digital Clock

Given below code is Simple Digital Clock. It accepts one input as 50 MHz clock and gives three output as Hour, Minute and Second. This code converts internally 50 MHz into 1 Hz Clock Frequency. In this code first process converts frequency from 50 MHz to 1 Hz. in the second process at every clock event second value will increment but up to 59 and then again zero. Same way Minute value will also increment after second value will reach to 59, but up to 59. Hour value will increment when minute value reaches to 59 and goes up to 23 and again goes to zero. In the last integer values of ss, mm and hr are converted into standard logic vector and assign to Second, Minute and Hour respectively. If you want to display this clock on your 7 segment or LCD display then you have write another code that accepts these inputs and generates equivalent output to be displayed.

Verilog Code for Electronic Combination Lock System using FSM

Sr. No.	Name of Pin	Direction	Width	Description
1	clk	Input	1	Clock Signal
2	rst	Input	1	Reset Signal
3	b0	Input	1	Input Digit “0”
4	b1	Input	1	Input Digit “1”
5	unlock	Output	1	Status for unlock

In this lock system, only two digits are used to unlock system. With the help of "0" and "1", the lock will be unlock but with specific pattern. This lock will be unlock with "01011" code. If this pattern will be identified by lock then lock will be become open and output unlock bit will be "1", otherwise lock remain close and unlock bit will be "0". This Lock System is developed using FSM and there are total six stages.

Verilog Code for Gray Counter

Gray code is one kind of binary number system where only one bit will change at a time. Today gray code is widely used in digital world. This will helpful for error correction and signal transmission. Gray counter is also useful in design and verification in VLSI domain. This code will generate gray code. Find out VHDL Code of Gray Counter here.

Implement Divide by 2, 4, 8 and 16 Counter using Flip-Flop

Counter plays a very important role into chip designing and verification. It is a very essential part of the VLSI Domain. Whenever we want to design or verify our design, most of the time we require slowing down frequencies. We can suppress this frequency using this counter by 2, 4, 8 or 16 times. Here circuit diagram and verilog code are given below.

Design 4-bit Linear Feedback Shift Register(LFSR) using Verilog Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. Find out VHDL Code Here.

Verilog Code for Sequence Detector "101101"

Here below verilog code for 6-Bit Sequence Detector "101101" is given. This code is implemented using FSM. FSM for this Sequence Detector is given in this image.

In this Sequence Detector, it will detect "101101" and it will give output as '1'.

Verilog Code for Johnson Counter

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find VHDL Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Verilog Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out VHDL Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

Design Round Robin Arbiter using Verilog FSM Coding with Variable Slice Period

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Req	Input	4	4 Request Signals
4	Grant	Output	4	4 Grant Signals

Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system. As the term is generally used, time slices are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. In this Arbiter, we have included one two bit counter. This counter will count no. of clock pulses for grant period of each request signal. In this if in between of counter, the request signal goes low, then grant will be given to other respective request signal and we can save that time slice.

Verilog Code for Vending Machine Using FSM

Sr. No.	Name of the Pin	Direction	Width	Description
1	Nw_pa	Output	1	News Paper Signal
2	Coin	Input	2	Only two Coins, 5 =2’b01 10 =2’b10 0 =2’b00
3	Clk	Input	1	Clock Signal
4	Rst	Input	1	Reset Signal

In this wending machine, it accepts only two coins, 5 point and 10 point. Whenever total of coins equal to 15 points, then nw_pa signal will go high and user will get news paper. It will not return any coin, if total of points exceeds 15 points.

Design Traffic Light Controller using Verilog FSM Coding and Verify with Test Bench

Given below code is design code for Traffic Light Controller using Finite State Machine(FSM). In this clk and rst_a are two input signal and n_lights, s_lights, e_lights and w_lights are 3 bit output signal. In output signal, "001" represents Green light, "010" represents Yellow light and "100" represents Red light. On the reset signal, design will enter into north state and start giving output after reset will go low. Design will turn on Green light for eight clock cycles and Yellow light for four clock cycles. Design will start with north, then goes into south, then east and finally into west and by this it will keep going.

Sr. No.	Name of the Pin	Direction	Width	Description
1	n_lights	Output	3	North Lights  (001 = Green, 010 = Yellow, 100 = Red)
2	s_lights	Output	3	South Lights (001 = Green, 010 = Yellow, 100 = Red)
3	e_lights	Output	3	Eight Lights  (001 = Green, 010 = Yellow, 100 = Red)
4	w_lights	Output	3	West Lights (001 = Green,  010 = Yellow, 100 = Red)
5	clk	Input	1	Clock Signal
6	Rst_a	Input	1	Reset Signal