VHDL Code for Synchronous FIFO

Sr. No.	Name of the Pin	Direction	Width	Description
1	Rst_a	Input	1	Reset Input
2	Clk	Input	1	Clock Input
3	we	Input	1	when high write into fifo and when low read from memory
5	Data_in	Input	8	Data Input
6	Data_out	Output	8	Data output
7	Full	Output	1	Fifo status 1 if fifo is full
8	Empty	Output	1	Fifo status 1 if fifo is empty

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity fifo is
  
  generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 8);         -- data_width

  port (
    data_in  : in  std_logic_vector(7 downto 0);  -- data
    data_out : out std_logic_vector(7 downto 0);  -- data_out
    clk      : in  std_logic;           -- clock signal
    rst      : in  std_logic;           -- reset signal
    we       : in  std_logic;           --write enable signal
    full     : out  std_logic;           -- full signal
    empty    : out std_logic);          -- empty signal

end fifo;

architecture beh of fifo is
constant depth : integer := 2**addr_width;  -- depth of ram

signal rd_point : std_logic_vector(addr_width-1 downto 0) := "0000";  -- read pointer

signal wr_point : std_logic_vector(addr_width-1 downto 0) := "0000";  -- write pointer

signal status : std_logic_vector(addr_width-1 downto 0) := "0000";  -- status pointer

signal ram_out : std_logic_vector(data_width-1 downto 0);  -- data out from ram

signal full_s,empty_s : std_logic;


component dual_port_ram 
generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 8);         -- data_width

 port (
    address1  : in  std_logic_vector(addr_width-1 downto 0);  -- address for port1
    data1     : in  std_logic_vector(data_width-1 downto 0);  -- data for port1
    we1       : in  std_logic;                     -- write enable for port1
    address2  : in  std_logic_vector(addr_width-1 downto 0);  -- address for port2
    data2     : in  std_logic_vector(data_width-1 downto 0);  -- data for port2
    we2       : in  std_logic;                     -- write enable for port 2
    data_out1 : out std_logic_vector(data_width-1 downto 0);  -- data_out for port 1
    data_out2 : out std_logic_vector(data_width-1 downto 0);  -- data out for port 2
    clk       : in  std_logic                     -- clock signal
   );                    -- reset signal

end component;
  
begin  -- beh


  full_s <= '1' when (status=(depth-1)) else '0';
  empty_s <= '1' when (status="0000") else '0';
  full<=full_s;
  empty<=empty_s;

  read_pointer: process (clk,rst)
  begin  -- process read_pointer
    if rst='1' then
      rd_point<="0000";
    elsif rising_edge(clk) then
      if we='0' then
        rd_point<=rd_point+'1';
      end if;
    end if;
  end process read_pointer;


  write_pointer: process (clk,rst)
  begin  -- process write_pointer
    if rst='1' then
      wr_point<="0000";
    elsif rising_edge(clk) then
      if we='1' then
        wr_point<=wr_point+'1';
      end if;
    end if;
  end process write_pointer;


  status_count: process (clk,rst)
  begin  -- process status
    if rst='1' then
      status<="0000";
    elsif rising_edge(clk) then
      if we='1' and status /= "1111" then
        status<=status+'1';
      elsif we='0' and status /= "0000" then
        status<=status-'1';        
      end if;
    end if;
  end process status_count;

assertions : process (we,full_s,empty_s)
begin
    if (full_s='1') then
       assert we='0' report "ram is full & you are overwritting to ram" severity error;
  elsif (empty_s='1') then
       assert we='1' report "ram is empty & you are reading the previos data from ram" severity error; 
  end if;
end process assertions;



  u1: dual_port_ram   
  generic map (
    addr_width => 4,          -- address width
    data_width => 8)         -- data_width

  port map (
      address1  => wr_point,
      data1     => data_in,
      we1       => we,
      clk       => clk,
      address2  => rd_point,
      data2     => data_in,
      data_out2 => data_out,
      data_out1 => open,
      we2       => we
      );
  

end beh;