Get Familiar with System Task in Verilog

There are special Tasks and Function in Verilog language which are used to generate input and output during simulation process. These special Tasks and Functions are always starts with $ sign, followed by Task/Function specifier. Synthesis tools ignore these system tasks and functions.

These System Tasks are classified as below

• Display Task
• $display, $write, $monitor, $strobe
• File I/O Task
• $fopen, $fclose, $fdisplay, $fstrobe, $fmonitor
• Timescale Task
• $time, $stime, $realtime
• Simulation Control Task
• $reset, $finish, $stop
  

All About Operators in Verilog

Every language has its own set of Operators. VHDL has its own operators, same way Verilog has own set of operators to perform several operation on inputs. If you have knowledge of operators in C or C++, then it is very easy to understand operators in Verilog. There are total ten types of operators in Verilog. Operators are depending on number of operands.

• Arithmetic
• Relational
• Equality
• Logical
• Bit-wise
• Reduction
• Shift
• Concatenation
• Replication
• Conditional

Quick Overview To Start Coding into Verilog

• Verilog is very popular Hardware Description language. It was introduced by Gateway Design Automation in 1984. In 1989, Cadence Design Systems purchased and put into public domain in 1990. In 1993, OVI enhanced the verilog language but that was not well accepted. IEEE standardized the Verilog HDL(IEEE 1364-1995) in 1995. In 2001, extension to verilog-95 submitted to IEEE and accepted verilog IEEE std 1364-2001. The revision of the language is also done in 2002 and 2005.

Data Types in Verilog Language

A Data Type is a classification of various class of Data, such as Real, Integer or Boolean. And It is important because it determines the value of that type; which operation can be done on values of that type; the real meaning of that data. Every language has its own Data Type.

In the same way, Verilog has it's own Data Types. There are mainly eight Data Types in Verilog which are listed below.

1. Value Set
2. Nets
3. Registers
4. Integers
5. Time
6. Real
7. Parameter
8. Arrays

Features of Verilog Language

• Verilog is case sensitive.

• In verilog, Keywords are defined in lower case.

• In Verilog, Most of the syntax is adopted from "C" language.

• Verilog can be used to model a digital circuit at Algorithm, RTL, Gate and Switch level.

• There is no concept of package in Verilog.

• It also supports advanced simulation features like TEXTIO, PLI, and UDPs.

Difference between $display and $strobe using Example in Verilog

Case 1 :

module case_1;
reg [31:0] data;

initial
 begin
  #20 data=50;
  $strobe("Strobe",$time,data);
  $display("display",$time,data);
  data=30;
 end

endmodule 

Ans. :

	Time	Data
$display	20	50
$strobe	20	30

---------------------------------------------------------------------------------------------

Interchange data without using third variable in Verilog

We can interchange value with the help of non-blocking statements.

always @ (a or b)

begin

a = 1;

b = 2;

#10;

Difference between Function and Task in Verilog

Function	Task
A Function must execute in one simulation time unit.	A Task may execute in non-zero simulation time.
A function can’t contain time-controlling event.	A task can contain time-controlling event.
A function can enable only function, not task.	A task can enable function and task.
A function must have at least one input argument.	A task can have zero or more arguments of any type.
A function returns a single value that is of bit or vector.	A task doesn’t return a value.