VHDL Code for Round Robin Arbiter with Variable Time Slice

Round Robin Arbiter will grant the request on circular basis. In this design code, there are four requests and four grant signals. This code will grant the request to first, second third and forth at the last. This code will grant the user request for four clock cycle and this time slice can be varied. This code can be modified for different time slices according to specification. Find Round Robin Arbiter with fixed time slice here.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity round_robin1 is
 
  port (
    clk   : in  std_logic;                      -- clock signal
    rst   : in  std_logic;                      -- reset signal
    req   : in  std_logic_vector(3 downto 0);   -- request vector
    grant : out std_logic_vector(3 downto 0));  -- grant vector

end round_robin1;

architecture beh of round_robin1 is

  type state is (s_ideal,s0,s1,s2,s3);          -- 4 states for 4 request users
  signal p_state : state := s_ideal;         -- present state
  signal count : std_logic_vector(1 downto 0) := "00";  -- counter for time
 

begin  -- beh

main: process (clk,rst,count)
begin  -- process main
  if rst='1' then
    count<="00";
    p_state<=s_ideal;
    grant<="0000";
  elsif rising_edge(clk) then
    case p_state is

      when s0 =>
        if req(0)='1' then
          if count="11" then
            if req(1)='1' then
              count<="00";
              p_state<=s1;
            elsif req(2)='1' then
              count<="00";
              p_state<=s2;
            elsif req(3)='1' then
              count<="00";
              p_state<=s3;
            else
              count<="00";
              p_state<=s0;
            end if;
          else
            count<=count+'1';
            grant<="0001";
            p_state<=s0;
          end if;
        elsif req(1)='1' then
          p_state<=s1;
          count<="00";
        elsif req(2)='1' then
          p_state<=s2;
          count<="00";
        elsif req(3)='1' then
          p_state<=s3;
          count<="00";
        else
          p_state<=s_ideal;
      end if;

      when s1 =>
      if req(1)='1' then
        if count="11" then
          if req(2)='1' then
            count<="00";
            p_state<=s2;
          elsif req(3)='1' then
            count<="00";
            p_state<=s3;
          elsif req(0)='1' then
            count<="00";
            p_state<=s0;
          else
            count<="00";
            p_state<=s1;
          end if;
        else
          count<=count+'1';
          grant<="0010";
          p_state<=s1;
        end if;
      elsif req(2)='1' then
        p_state<=s2;
        count<="00";
      elsif req(3)='1' then
        p_state<=s3;
        count<="00";
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

      when s2 =>
      if req(2)='1' then
        if count="11" then
          if req(3)='1' then
            count<="00";
            p_state<=s3;
          elsif req(0)='1' then
            count<="00";
            p_state<=s0;
          elsif req(1)='1' then
            count<="00";
            p_state<=s1;
          else
            count<="00";
            p_state<=s2;
          end if;
        else
          count<=count+'1';
          grant<="0100";
          p_state<=s2;
        end if;
      elsif req(3)='1' then
        p_state<=s3;
        count<="00";
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      elsif req(1)='1' then
        p_state<=s1;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

      when s3 =>

      if req(3)='1' then
        if count="11" then
          if req(0)='1' then
            count<="00";
            p_state<=s0;
          elsif req(1)='1' then
            count<="00";
            p_state<=s1;
          elsif req(2)='1' then
            count<="00";
            p_state<=s2;
          else
            count<="00";
            p_state<=s3;
          end if;
        else
          count<=count+'1';
          grant<="1000";
          p_state<=s3;
        end if;
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      elsif req(1)='1' then
        p_state<=s1;
        count<="00";
      elsif req(2)='1' then
        p_state<=s2;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

     
      when others =>
        if req(0)='1' then
          p_state<=s0;
          count<="00";
        elsif req(1)='1' then
          p_state<=s1;
          count<="00";
        elsif req(2)='1' then
          p_state<=s2;
          count<="00";
        elsif req(3)='1' then
          p_state<=s3;
          count<="00";
        else
            p_state<=s_ideal;
            count<="00";
            grant<="0000";
        end if;
    end case;
  end if;
end process main;

end beh;

Test Bench for 1-Bit Full-Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_con_tst is
  
end full_adder_con_tst;
 architecture beh of full_adder_con_tst is
   component full_adder_con
       port (
    a,b,c: in  std_logic;   -- inputs
    sum,ca: out std_logic);  -- outputs

end component;
    signal a_s,b_s,c_s : std_logic;  -- signals
    signal sum_s,ca_s : std_logic;  -- output signals
 begin  -- beh

u1 : full_adder_con port map (
  a => a_s,
   b => b_s,
   c => c_s,
   sum => sum_s,
  ca => ca_s);

tst_p: process
   begin
      a_s<='0';
       b_s<='0';
       c_s<='0';
       wait for 100 ns;
       a_s<='0';
       b_s<='0';
       c_s<='1';
       wait for 100 ns;
       a_s<='0';
       b_s<='1';
       c_s<='0';
       wait for 100 ns;
       a_s<='0';
       b_s<='1';
       c_s<='1';
       wait for 100 ns;
       a_s<='1';
       b_s<='0';
       c_s<='0';
       wait for 100 ns;
       a_s<='1';
       b_s<='0';
       c_s<='1';
       wait for 100 ns;
       a_s<='1';
       b_s<='1';
       c_s<='0';
       wait for 100 ns;
       a_s<='1';
       b_s<='1';
       c_s<='1';
       wait for 100 ns;
    end process;
 end beh;

VHDL Code for 1-Bit Full Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_con is

  port (
    a, b, c : in  std_logic;            -- inputs
    sum, ca : out std_logic);           -- sum & carry

end full_adder_con;

architecture beh of full_adder_con is

begin  -- beh

      sum <= '0' when a = '0' and b = '0' and c ='0' else
             '1' when a = '0' and b = '0' and c ='1' else
             '1' when a = '0' and b = '1' and c ='0' else
             '0' when a = '0' and b = '1' and c ='1' else
             '1' when a = '1' and b = '0' and c ='0' else
             '0' when a = '1' and b = '0' and c ='1' else
             '0' when a = '1' and b = '1' and c ='0' else
             '1' when a = '1' and b = '1' and c ='1' else
             'X';
     ca   <= '0' when a = '0' and b = '0' and c ='0' else
             '0' when a = '0' and b = '0' and c ='1' else
             '0' when a = '0' and b = '1' and c ='0' else
             '1' when a = '0' and b = '1' and c ='1' else
             '0' when a = '1' and b = '0' and c ='0' else
             '1' when a = '1' and b = '0' and c ='1' else
             '1' when a = '1' and b = '1' and c ='0' else
             '1' when a = '1' and b = '1' and c ='1' else
             'X';

end beh;

Test Bench for 4x1 Multiplexer in VHDL

Find out Design code of 4x1 Mux here.

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1_seq_tst is
  
end mux4x1_seq_tst;
 architecture beh of mux4x1_seq_tst is
   component mux4x1_seq
   port (
    ip0 : in  std_logic;   -- input pin
    ip1 : in  std_logic;   -- input pin
    ip2 : in  std_logic;   -- input pin
    ip3 : in  std_logic;   -- input pin
    s : in std_logic_vector(0 to 1);     --select line
    op : out std_logic);  -- output 

end component;
    signal  ip0_s :  std_logic;   -- input signal
   signal  ip1_s :  std_logic;   -- input signal
   signal ip2_s :  std_logic;   -- input signal
   signal ip3_s :  std_logic;   -- input signal
   signal  s_s :  std_logic_vector(0 to 1);     --msb of select line signal
   signal  op_s :  std_logic;  -- output siganl
 begin  -- beh

u1 : mux4x1_seq port map (
  ip0 => ip0_s,
   ip1 => ip1_s,
   ip2 => ip2_s,
   ip3 => ip3_s,
   s => s_s,
  op => op_s);
tst_p: process
   begin
      ip0_s<='1';
       ip1_s<='0';
       ip2_s<='0';
       ip3_s<='0';
       s_s<="00";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='1';
        ip2_s<='0';
        ip3_s<='0';
       s_s<="10";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='0';
        ip2_s<='1';
        ip3_s<='0';
       s_s<="01";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='0';
        ip2_s<='0';
        ip3_s<='1';
       s_s<="11";
       wait for 100 ns;
   end process;

 end beh;

VHDL Code for 4x1 Multiplexer

Find out Test Bench for 4x1 Mux here.

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1_seq is
  
port (
  ip0, ip1, ip2, ip3 : in  std_logic;
  s                  : in  std_logic_vector(0 to 1);
  op                 : out std_logic);
end mux4x1_seq;

architecture beh of mux4x1_seq is

begin  -- beh
p_mux : process (ip0,ip1,ip2,ip3,s)
  variable temp : std_logic;
  begin
    case s is
      when "00" => temp := ip0 ;
      when "01" => temp := ip1;
      when "10" => temp := ip2;
      when others => temp := ip3;
    end case;
    op <= temp;
  end process p_mux;

end beh;

Test Bench for 1x4 DeMultiplexer in VHDL

Find out DeMultiplexer Code here.

library ieee;
use ieee.std_logic_1164.all;

entity dmux1x4_seq_tst is
  
end dmux1x4_seq_tst;
 architecture beh of dmux1x4_seq_tst is
   component dmux1x4_seq
    port (
    s  : in  std_logic_vector(1 downto 0);  -- select lines
    i : in std_logic;                       -- input
   op  : out  std_logic_vector(3 downto 0)  -- outputs
   );

end component;
    signal ip_s : std_logic;  -- signals
    signal op_s : std_logic_vector(3 downto 0);  -- output signals
    signal s_s : std_logic_vector(1 downto 0);  -- select line signals
 begin  -- beh

u1 : dmux1x4_seq port map (
  i => ip_s,
  s => s_s,
  op => op_s);

tst_p: process
   begin
      ip_s<='1';
       s_s<="00";
       wait for 100 ns;
       ip_s<='1';
       s_s<="01";
       wait for 100 ns;
       ip_s<='1';
       s_s<="10";
       wait for 100 ns;
       ip_s<='1';
       s_s<="11";
       wait for 100 ns;
    end process;

 end beh;

VHDL Code for 1x4 DeMultiplexer

Function of DeMultiplexer is opposite of Multiplexer. It has one input and several output based on control signal. Find out Test Bench here.

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library ieee;
use ieee.std_logic_1164.all;

entity dmux1x4_seq is
  
  port (
    i : in  std_logic;                      -- input lines
    s : in  std_logic_vector(1 downto 0);   -- select lines
    op : out std_logic_vector(3 downto 0));

end dmux1x4_seq;

architecture beh of dmux1x4_seq is
  
begin  -- beh

u1 : process (i,s)
 variable temp : std_logic_vector(0 to 3);
  begin  -- process u1
    case s is
      when "00" => temp := "000"&i;
      when "01" => temp := "00"&i&'0';
      when "10" => temp := '0'&i&"00";
      when "11" => temp := i&"000";
      when others => null;
    end case;
    op <= temp;
  end process u1;
end beh;

Test Bench for 8x3 Encoder in VHDL

Find out VHDL code for 8x3 Encoder here.

library ieee;
use ieee.std_logic_1164.all;

entity enco8x3_seq_tst is
  
end enco8x3_seq_tst;
 architecture beh of enco8x3_seq_tst is
   component enco8x3_seq
       port (
    i: in  std_logic_vector(7 downto 0);   -- inputs
    o: out std_logic_vector(2 downto 0));  -- outputs

end component;
    signal i_s : std_logic_vector(7 downto 0);  -- signals
    signal o_s : std_logic_vector(2 downto 0);  -- output signals
 begin  -- beh

u1 : enco8x3_seq port map (
  i => i_s,
  o => o_s);

tst_p: process
   begin
       i_s<="00000001";
       wait for 100 ns;
       i_s<="00000010";
       wait for 100 ns;
       i_s<="00000100";
       wait for 100 ns;
       i_s<="00001000";
       wait for 100 ns;
       i_s<="00010000";
       wait for 100 ns;
       i_s<="00100000";
       wait for 100 ns;
       i_s<="01000000";
       wait for 100 ns;
       i_s<="10000000";
       wait for 100 ns;
    end process;
 end beh;

VHDL Code for 8x3 Encoder

Encoder is a combinational circuit which converts set of signal into equivalent code. Function is exactly opposite of Decoder. Find out Test Bench for 8x3 Encoder here.

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library ieee;
use ieee.std_logic_1164.all;


entity enco8x3_seq is
  
  port (
    i : in  std_logic_vector(7 downto 0);  -- inputs
    o : out std_logic_vector(2 downto 0));  -- outputs

end enco8x3_seq;


architecture beh of enco8x3_seq is

begin  -- beh

  enco : process (i)
  variable temp : std_logic_vector(2 downto 0);
  begin
    case i is
      when "00000001" => temp := "000";
      when "00000010" => temp := "001";
      when "00000100" => temp := "010";
      when "00001000" => temp := "011" ;
      when "00010000" => temp := "100";
      when "00100000" => temp := "101";
      when "01000000" => temp := "110";
      when "10000000" => temp := "111";
      when others => temp := "XXX";
    end case;
    o <= temp;
  end process enco;

end beh;

VHDL Code for 3x8 Decoder

A Decoder is a combinational logic circuit which converts code into a set of signals. It is exactly opposite of Encoder. It is mostly used to generate selection or enable line in a digital circuit. Find out Test Bench for 3x8 Decoder in VHDL over here.

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library ieee;
use ieee.std_logic_1164.all;

entity deco3x8_seq is
  
  port (
    ip : in  std_logic_vector(2 downto 0);   -- input
    op : out std_logic_vector(7 downto 0));  -- output

end deco3x8_seq;

architecture beh of deco3x8_seq is

begin  -- beh

deco : process (ip)
  variable temp : std_logic_vector(7 downto 0);
  begin
    case ip is
      when "000" => temp := "00000001";
      when "001" => temp := "00000010";
      when "010" => temp := "00000100";
      when "011" => temp := "00001000";
      when "100" => temp := "00010000";
      when "101" => temp := "00100000";
      when "110" => temp := "01000000";
      when "111" => temp := "10000000";
      when others => temp := "XXXXXXXX";
    end case;
    op <= temp;
 end process deco;
end beh;

Test Bench for 3x8 Decoder in VHDL

Find out VHDL code for 3x8 Decoder here.

library ieee;
use ieee.std_logic_1164.all;

entity deco3x8_seq_tst is

end deco3x8_seq_tst;
 architecture beh of deco3x8_seq_tst is
   component deco3x8_seq
       port (
    ip: in  std_logic_vector(2 downto 0);   -- inputs
    op: out std_logic_vector(7 downto 0));  -- outputs

end component;
    signal ip_s : std_logic_vector(2 downto 0);  -- signals
    signal op_s : std_logic_vector(7 downto 0);  -- output signals
 begin  -- beh

u1 : deco3x8_seq port map (
  ip => ip_s,
  op => op_s);

tst_p: process
   begin
      ip_s<="000";
       wait for 100 ns;
       ip_s<="001";
       wait for 100 ns;
       ip_s<="010";
       wait for 100 ns;
       ip_s<="011";
       wait for 100 ns;
       ip_s<="100";
       wait for 100 ns;
       ip_s<="101";
       wait for 100 ns;
       ip_s<="110";
       wait for 100 ns;
       ip_s<="111";
       wait for 100 ns;
    end process;
 end beh;