VHDL Code for 4-bit Up-Down Counter with Pre-Load

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity up_counter_sync_preload is
  
  port(clk, rst_a,load : in std_logic; 
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0)); 

end up_counter_sync_preload; 

architecture archi of up_counter_sync_preload is 

   begin  
    process (clk, rst_a)
      variable tmp,cnt : std_logic_vector(3 downto 0):="0000";
      begin 
        if (rst_a='1') then 
          tmp := "0000"; 
       elsif (clk'event and clk='1') then
          cnt:=tmp; 
          if (load='1') then
          tmp := ip;
           else 
          tmp := tmp + '1';
          end if;
          assert (tmp-cnt="0001") report "count differ by 1 violate" severity warning;
      end if;
          q<=tmp;
    end process;
    

end archi;