Design 4 bit Magnitude Comprator using Verilog and Verify with Test Bench

This design accepts two four bit inputs 'a' and 'b' and generates three one bit outputs 'eq', 'gt' and 'lt'. If both inputs are same then 'eq' bit will be high and other two outputs will be low. If 'a' is greater than 'b' then 'gt' will be high and other two outputs will be low. Same way if 'a' is less than 'b' then 'lt' output will go high and other two output will go low.

module comparator(a,b,eq,lt,gt);

input [3:0] a,b;

output reg eq,lt,gt;

always @(a,b)
begin
 if (a==b)
 begin
  eq = 1'b1;
  lt = 1'b0;
  gt = 1'b0;
 end
 else if (a>b)
 begin
  eq = 1'b0;
  lt = 1'b0;
  gt = 1'b1;
 end
 else
 begin
  eq = 1'b0;
  lt = 1'b1;
  gt = 1'b0;
 end
end 
endmodule

This design is synthesized using Xilinx Vivado and RTL view of this magnitude comparator is given below.

RTL view of Magnitude Comparator

Test Bench Code for this Magnitude Comparator is given below.

`timescale 1ns/1ps

module comparator_tst;
  reg [3:0] a,b;
  wire eq,lt,gt;
  
  comparator DUT (a,b,eq,lt,gt);
  
  initial
  begin
   a = 4'b1100;
   b = 4'b1100;
   #10;
 
   a = 4'b0100;
   b = 4'b1100;
   #10;
 
   a = 4'b1111;
   b = 4'b1100;
   #10;
 
   a = 4'b0000;
   b = 4'b0000;
   #10;
   $stop;
  end
endmodule

Test Bench is simulated using Xilinx Vivado and waveform is shown below.

Waveform for Magnitude Comparator