VHDL Code for Parity Generator using Function

When valid_in is ‘1’ it will accept serial input and that serial input goes for parallel output. After receiving eight bit of serial input this block converts the serial input to parallel output. Valid_out signal goes ‘1’ after receiving eight bytes of serial data & gives parallel data on the data_o. After valid_out goes high parity_out signal gives parity of the input data. Valid_out signal goes high on each eighth clock cycle & remain high for one cycle.

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity parity_generator is 

  port( clk       :in std_logic;    --clock signal
        d_in      :in std_logic;    --serial data input
        valid_in  :in std_logic;    --valid input signal
        rst_a     :in  std_logic;   --reset signal
        valid_out :out std_logic;   --valid output signal
        parity_out:out std_logic;   --parity check signal
        data_o        :out std_logic_vector(7 downto 0)); --parallel data output
       
end parity_generator; 


architecture archi of parity_generator is

--fuction to check parity of output data
function parity_chk (constant i : std_logic_vector(7 downto 0)) 
    return std_logic is 
    begin
    return (i(0) xor i(1) xor i(2) xor i(3) xor i(4) xor i(5) xor i(6) xor i(7));
end parity_chk;

 subtype cnt8 is integer range 0 to 8; 

 
    --signal tmp: std_logic_vector(7 downto 0) := "00000000";
    --signal cnt : cnt8 := 0; -- counter to count 8 serial input data.
  begin 
process (clk,rst_a)
  variable tmp: std_logic_vector(7 downto 0);
  variable cnt: cnt8 := 0;
  begin  
    if (rst_a = '1') then
      data_o<="00000000";
      valid_out<='0';
      parity_out<='-';
    elsif (clk'event and clk='1') then
      if(valid_in='1') then
        tmp:=tmp(6 downto 0)& d_in;
        cnt:=cnt+1;
      if(cnt = 8) then
        valid_out<='1';
        data_o<=tmp;
        parity_out <= parity_chk(tmp);
        cnt:=0;
      else 
        valid_out <= '0';
        parity_out <= '-';
        data_o<="XXXXXXXX";  
      end if;
    end if;
  end if;
end process;
end archi;