VHDL Code for Round Robin Arbiter with Variable Time Slice

Round Robin Arbiter will grant the request on circular basis. In this design code, there are four requests and four grant signals. This code will grant the request to first, second third and forth at the last. This code will grant the user request for four clock cycle and this time slice can be varied. This code can be modified for different time slices according to specification. Find Round Robin Arbiter with fixed time slice here.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity round_robin1 is
 
  port (
    clk   : in  std_logic;                      -- clock signal
    rst   : in  std_logic;                      -- reset signal
    req   : in  std_logic_vector(3 downto 0);   -- request vector
    grant : out std_logic_vector(3 downto 0));  -- grant vector

end round_robin1;

architecture beh of round_robin1 is

  type state is (s_ideal,s0,s1,s2,s3);          -- 4 states for 4 request users
  signal p_state : state := s_ideal;         -- present state
  signal count : std_logic_vector(1 downto 0) := "00";  -- counter for time
 

begin  -- beh

main: process (clk,rst,count)
begin  -- process main
  if rst='1' then
    count<="00";
    p_state<=s_ideal;
    grant<="0000";
  elsif rising_edge(clk) then
    case p_state is

      when s0 =>
        if req(0)='1' then
          if count="11" then
            if req(1)='1' then
              count<="00";
              p_state<=s1;
            elsif req(2)='1' then
              count<="00";
              p_state<=s2;
            elsif req(3)='1' then
              count<="00";
              p_state<=s3;
            else
              count<="00";
              p_state<=s0;
            end if;
          else
            count<=count+'1';
            grant<="0001";
            p_state<=s0;
          end if;
        elsif req(1)='1' then
          p_state<=s1;
          count<="00";
        elsif req(2)='1' then
          p_state<=s2;
          count<="00";
        elsif req(3)='1' then
          p_state<=s3;
          count<="00";
        else
          p_state<=s_ideal;
      end if;

      when s1 =>
      if req(1)='1' then
        if count="11" then
          if req(2)='1' then
            count<="00";
            p_state<=s2;
          elsif req(3)='1' then
            count<="00";
            p_state<=s3;
          elsif req(0)='1' then
            count<="00";
            p_state<=s0;
          else
            count<="00";
            p_state<=s1;
          end if;
        else
          count<=count+'1';
          grant<="0010";
          p_state<=s1;
        end if;
      elsif req(2)='1' then
        p_state<=s2;
        count<="00";
      elsif req(3)='1' then
        p_state<=s3;
        count<="00";
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

      when s2 =>
      if req(2)='1' then
        if count="11" then
          if req(3)='1' then
            count<="00";
            p_state<=s3;
          elsif req(0)='1' then
            count<="00";
            p_state<=s0;
          elsif req(1)='1' then
            count<="00";
            p_state<=s1;
          else
            count<="00";
            p_state<=s2;
          end if;
        else
          count<=count+'1';
          grant<="0100";
          p_state<=s2;
        end if;
      elsif req(3)='1' then
        p_state<=s3;
        count<="00";
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      elsif req(1)='1' then
        p_state<=s1;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

      when s3 =>

      if req(3)='1' then
        if count="11" then
          if req(0)='1' then
            count<="00";
            p_state<=s0;
          elsif req(1)='1' then
            count<="00";
            p_state<=s1;
          elsif req(2)='1' then
            count<="00";
            p_state<=s2;
          else
            count<="00";
            p_state<=s3;
          end if;
        else
          count<=count+'1';
          grant<="1000";
          p_state<=s3;
        end if;
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      elsif req(1)='1' then
        p_state<=s1;
        count<="00";
      elsif req(2)='1' then
        p_state<=s2;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

     
      when others =>
        if req(0)='1' then
          p_state<=s0;
          count<="00";
        elsif req(1)='1' then
          p_state<=s1;
          count<="00";
        elsif req(2)='1' then
          p_state<=s2;
          count<="00";
        elsif req(3)='1' then
          p_state<=s3;
          count<="00";
        else
            p_state<=s_ideal;
            count<="00";
            grant<="0000";
        end if;
    end case;
  end if;
end process main;

end beh;