Easy UVM (Universal Verification Methodology) Tutorial

UVM stands for Universal Verification Methodology. It is standard methodology to verify Integrated Circuits. UVM is derived from OVM, Open Verification Methodology. UVM is developed by Accellera with the support of Aldec, Cadence, Mentor Graphics and Synopsys. UVM is based on System Verilog language. With the help of UVM, engineers are able to create an efficient verification environment. It is portable from one project to another. Due to portability, engineers can reuse testbench from previous projects and modify different components as per their need. UVM easy tutorial is shown below. It is available on YouTube. It is developed by John Aynsley from Doulos. There are twenty videos. After watching this tutorial, overall picture of UVM will be cleared. 

Verilog Code for (7,4) Systematic Hamming Encoder

Hamming code is useful in Error Correction in Linear Block Code. This code will encode four bits of data and generate seven bits of code by adding three bits as parity bits. It was introduced by Richard W. Hamming. This algorithm can detect one and two bit error and can correct one bit error. Given below code will generate (7,4) Systematic Hamming Encoder. This encoder will use Least Significant 4 bits as data inputs and Most 3 significant bits as a parity bits.

Get VHDL Code.

Design 4 bit Magnitude Comprator using Verilog and Verify with Test Bench

This design accepts two four bit inputs 'a' and 'b' and generates three one bit outputs 'eq', 'gt' and 'lt'. If both inputs are same then 'eq' bit will be high and other two outputs will be low. If 'a' is greater than 'b' then 'gt' will be high and other two outputs will be low. Same way if 'a' is less than 'b' then 'lt' output will go high and other two output will go low.

Design Traffic Light Controller using Verilog FSM Coding and Verify with Test Bench

Given below code is design code for Traffic Light Controller using Finite State Machine(FSM). In this clk and rst_a are two input signal and n_lights, s_lights, e_lights and w_lights are 3 bit output signal. In output signal, "001" represents Green light, "010" represents Yellow light and "100" represents Red light. On the reset signal, design will enter into north state and start giving output after reset will go low. Design will turn on Green light for eight clock cycles and Yellow light for four clock cycles. Design will start with north, then goes into south, then east and finally into west and by this it will keep going.

Sr. No.	Name of the Pin	Direction	Width	Description
1	n_lights	Output	3	North Lights  (001 = Green, 010 = Yellow, 100 = Red)
2	s_lights	Output	3	South Lights (001 = Green, 010 = Yellow, 100 = Red)
3	e_lights	Output	3	Eight Lights  (001 = Green, 010 = Yellow, 100 = Red)
4	w_lights	Output	3	West Lights (001 = Green,  010 = Yellow, 100 = Red)
5	clk	Input	1	Clock Signal
6	Rst_a	Input	1	Reset Signal

Design 8x3 Priority Encoder in Verilog Coding and Verify with TestBench

Priority Encoder allocates priority to each input. Design and Test Bench code of 8x3 Priority Encoder is given below. Output are set according to priorities of inputs. So if input with higher priority is present then inputs with lower priorities are ignored and generates output according to highest priority input.

S. No.	Name	Direction	Width	Remark
1.	D_in	IN	8 bit	Input lines
3.	D_out	OUT	3 bit	Output lines