Setup Time and Hold Time

These two parameters are associated with Flip-Flop. Setup Time and Hold Time are two most important factors in Synchronous Design in VLSI Domain. If either of them is violated then Flip-Flop will not give proper output. 

Setup Time: - It’s a time interval before the Clock signal is triggered, where Data signal should be stable. So, that Data is easily sampled by the Flip-Flop.

Difference between Flip-Flop and Latch

Flip-Flop	Latch
Flip-Flop is Edge sensitive device.	Latch is Level sensitive device.
In Flip-Flop, output will change on rising or falling edge of clock signal.	In Latch, if Enable/Clock signal is high then output will change accordingly input.
So, we can say that Flip-Flop is a Synchronous version of Latch.	So, we can say that Latch is Asynchronous device.
Flip-Flop based design creates less timing problems.	Latch based design creates more timing problems.
In design Flip-Flop takes more area compared to Latch.	In design Latch takes less area compared to Flip-Flop.
In design Flip-Flop consumes more power compare to Latch.	In design Latch consumes less power compare to Flip-Flop.

Shift Operators in VHDL

Shift operators are playing very important role in VHDL language. It is very usefull to shift or rotate digits of binary numbers.

There are total six shifting operators in VHDL language.

•  sll

• It means Logical Shift Left.

• It shifts the elements in the array by n places to left and fill vacanted positions with "0".

• Ex

• "1000_1010" sll 3 will give "0101_0000".

• "1000_1010" sll -2 will give "0010_0010".