VHDL Code for 16x9 Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	addr	Input	4	Input address i.e. address bus
2	oe	input	1	output enable
3	wr_l	Input	1	If 0 write in to memory & if 1 read from memory
4	data	Input/Output	9	Output read/write from/to memory i.e. bidirectional data bus MSB is parity bit

Memory Code

library IEEE;
use IEEE.std_logic_1164.all;

entity memory is
 port (data : inout std_logic_vector (8 downto 0);  -- databus
         
   addr : in std_logic_vector (3 downto 0);     -- address bus
         
  oe, wr_l, clk : in std_logic);             -- control signals

end entity;

architecture arch  of memory is

  ----------------------------------------
  -- Instantiation of D flipflop component
  ----------------------------------------
  component d_ff is
    port (d_in , en , clk : in std_logic;
          q : out std_logic);
  end component;

  -------------------------------------
  -- Instantiation of Decoder component
  -------------------------------------
  component decoder_4x16 is

    port (
      i : in  std_logic_vector (3 downto 0);   -- input ports
      o : out std_logic_vector (15 downto 0));  -- output ports

  end component;

  -----------------------------------
  -- Instantiation of Tristate buffer
  -----------------------------------
  component tri_state is

    port (
      en    : in  std_logic;
      d_in  : in  std_logic_vector (8 downto 0);
      d_out : out std_logic_vector (8 downto 0));

  end component;
-------------------------------
-- function to calculate parity
-------------------------------
   function parity_gen_func (par : in std_logic_vector (7 downto 0)) return std_logic is
  begin

  return par(0)xor par(1)xor par(2)xor par(3)xor par(4)xor par(5)xor par(6)xor par(7);

  end parity_gen_func;

 
  type temp is array ( 15 downto 0) of std_logic_vector (8 downto 0);

  signal row : std_logic_vector (15 downto 0);  -- temporary row address container

  signal d_ff_out : temp;               -- temporary data

  signal en_tri_state : std_logic_vector (15 downto 0);  --enable signal for
                                                         --tristate buffer

begin  -- arch

  --------------------------
  -- Memory address decoding
  --------------------------
  dec: decoder_4x16 port map (i => addr,
                             o => row);

  -----------------------------------------------
  --Selecting flipflop for row and column address
  -----------------------------------------------
 
  generate_dff_coloumn:  for i in 7 downto 0 generate
    generate_dff_row: For j in 15 downto 0 generate
    dff: d_ff port map (
      d_in => data(i),
      en => row(j),
      clk => clk,
      q => d_ff_out(j)(i));
  end generate generate_dff_row;
end generate generate_dff_coloumn;

  generate_row_8 :  for i in 15 downto 0 generate
    assert data(8)=parity_gen_func(data(7 downto 0)) report "parity error" severity error;
    dff1 : d_ff port map (
                              d_in => data(8),
                              en => row(i),
                              clk => clk,
                              q => d_ff_out(i)(8));
      end generate generate_row_8;


    --------------------------------------------------------
    --Tristate buffer for input/output operation for data bus
    --------------------------------------------------------
    generate_tri_state: for i in 15 downto 0 generate
      tri_state_buffer: tri_state port map (
        en => en_tri_state(i),
        d_in => d_ff_out(i),
        d_out => data);
    end generate generate_tri_state;

    -----------------------------------
    --Enable signal for tristate buffer
    -----------------------------------
    process(row,wr_l,oe)
    begin
      for i in 15 downto 0 loop
        en_tri_state(i) <= ((oe and wr_l) and (row(i)));
    end loop;
 
    end process;
 
end arch ;

D_ff Code

library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff is
port (d_in , en , clk : in std_logic;
 q : out std_logic);
end entity;

architecture arch of d_ff is
begin
  process(clk,en,d_in)
    begin
    if (en='1') then
      if (clk'event and clk='1') then 
        q <= d_in;
      end if;
    end if;
  end process;
end arch;

Decoder_4x16 Code

library ieee;
use ieee.std_logic_1164.all;

entity decoder_4x16 is
  
  port (
    i : in  std_logic_vector (3 downto 0);   -- input ports
    o : out std_logic_vector (15 downto 0));  -- output ports

end decoder_4x16;

architecture arch of decoder_4x16 is

begin  -- deoder_concr_arch

  with i select
    o <=
    "0000000000000001" when "0000",
    "0000000000000010" when "0001",
    "0000000000000100" when "0010",
    "0000000000001000" when "0011",
    "0000000000010000" when "0100",
    "0000000000100000" when "0101",
    "0000000001000000" when "0110",
    "0000000010000000" when "0111",
    "0000000100000000" when "1000",
    "0000001000000000" when "1001",
    "0000010000000000" when "1010",
    "0000100000000000" when "1011",
    "0001000000000000" when "1100",
    "0010000000000000" when "1101",
    "0100000000000000" when "1110",
    "1000000000000000" when "1111",
    "XXXXXXXXXXXXXXXX" when others;

end arch;

Tri-state Code

library IEEE;
use IEEE.std_logic_1164.all;

entity tri_state is
  
  port (
    en    : in  std_logic;
    d_in  : in  std_logic_vector (8 downto 0);
    d_out : out std_logic_vector (8 downto 0));

end tri_state;

architecture arch of tri_state is

begin  -- arch

    with en select
    d_out <=
    d_in when '1',
    "ZZZZZZZZZ" when '0',
    "XXXXXXXXX" when others;

end arch;