Design a Constant Divider using VHDL Coding.

Constant Divider circuit accepts an input of 8 bit wide and divides it by constant value 53. The divider circuit will generate two output values as remainder and quotient. As we know that the division operator is not synthesizable, so division is done by repetitive subtraction method. As an example of input is 108, the remainder is 2 and quotient is 2 while if input is 20, remainder is 20 and quotient is 0. In this design Inp is input with 8 bit long, Remi and Quo are two output signals with 6-bit and 3-bit long respectively. Here bit lengths of Remi and Quo are decided as per getting maximum value. Divider is constant which is 8 bit long and value is "00110101". Binary value of 53 is "00110101".

Design 4-bit Linear Feedback Shift Register (LFSR) using VHDL Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. It is used for State Encoding. It is also used to generate random numbers. Find out Verilog code here.

Excitation and Characteristic Table of SR Flip Flop

The basic SR Flip-Flop is shown below. The inputs, labeled S and R are used to SET and RESET the device, respectively. The outputs Q and Q’ are complementary. Because the Flip-Flop is unclocked, any change to the inputs will produce a change at the outputs. An invalid state occurs when both inputs are low; thus, the inputs should be kept high except when the Flip-Flop is to be set or cleared. Note that there are other implementations for a latch. Here we are showing a NAND implementation.

Design 8 bit Ripple Carry Adder using VHDL Coding and Verify using Test Bench

Given below code will generate 8 bit output as sum and 1 bit carry as cout.  it also takes two 8 bit inputs as a and b, and one input carry as cin. This code is implemented in VHDL by structural style. Predefined full adder code is mapped into this ripple carry adder. Full Adder code can be found here. Carry is generated by adding each bit of two inputs and propagated to next bit of inputs. If carry is generated by adding seventh bits and previous carry, then cout bit goes high.

Design Gray Counter using VHDL Coding and Verify with Test Bench

Given below code is about Gray Counter in VHDL. In a gray code only one bit changes at a one time. This design code has two inputs clock and reset signals and one four bit output that will generate gray code. In the first if rst signal is high then output will be zero and as soon as rst will go low, on the rising edge of clk, design will generate four bit gray code and continue to generate at every rising edge of clk signal. This design code can be upgraded and put binary numbers as a input and this design will work as binary to gray code converter. Find out Verilog Code of Gray Counter here.

Design BCD to 7-Segment Decoder using Verilog Coding

Given below Verilog code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find VHDL Code here.

Common Cathode Seven Segment Display

Design 4 bit Magnitude Comprator using Verilog and Verify with Test Bench

This design accepts two four bit inputs 'a' and 'b' and generates three one bit outputs 'eq', 'gt' and 'lt'. If both inputs are same then 'eq' bit will be high and other two outputs will be low. If 'a' is greater than 'b' then 'gt' will be high and other two outputs will be low. Same way if 'a' is less than 'b' then 'lt' output will go high and other two output will go low.

All About Operators in Verilog

Every language has its own set of Operators. VHDL has its own operators, same way Verilog has own set of operators to perform several operation on inputs. If you have knowledge of operators in C or C++, then it is very easy to understand operators in Verilog. There are total ten types of operators in Verilog. Operators are depending on number of operands.

• Arithmetic
• Relational
• Equality
• Logical
• Bit-wise
• Reduction
• Shift
• Concatenation
• Replication
• Conditional

Quick Overview To Start Coding into Verilog

• Verilog is very popular Hardware Description language. It was introduced by Gateway Design Automation in 1984. In 1989, Cadence Design Systems purchased and put into public domain in 1990. In 1993, OVI enhanced the verilog language but that was not well accepted. IEEE standardized the Verilog HDL(IEEE 1364-1995) in 1995. In 2001, extension to verilog-95 submitted to IEEE and accepted verilog IEEE std 1364-2001. The revision of the language is also done in 2002 and 2005.

A Brief Overview Of Data Type in VHDL.

VHDL is strongly typed language and it supports a variety of Data Types and Operators. Users can also define their own data types and operators in user defined packages. There are three basic classes to define data objects in VHDL language.

• Signal : It represents interconnections that connect components and parts.
• Variable : It is used for local storage within process.
• Constant : It is used to declare a fixed value.

The data object can be a scalar or an array (one dimensional as well as multi dimensional).

Get Knowledge of Operators in VHDL with Examples

VHDL has wide range of Operators, which can be grouped into following

• Logical Operators
• Relational Operators
• Shift Operators.
• Miscellaneous Operators

Get Knowledge of Delay Types in VHDL

In VHDL, delays are specified only in signal assignment not in variable assignment. Delays are not synthesizable. There are two types of delay in VHDL Language.

1. Transport Delay
2. Inertial Delay

• Transport Delay : It is the delay model just delay the signal or change the value of the signal by the time specified in the after clause. It is the characteristic of the hardware elements that exhibits infinite frequency response. Any pulse is transmitted no matter how small it is.

Design BCD to 7-Segment Decoder using VHDL Code

Given below VHDL code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find out Verilog Code here.

Common Cathode Seven Segment Display

Design Johnson Counter and Test with Test Bench using VHDL Code

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find out Verilog Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

VHDL Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out Verilog Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

Verilog and VHDL Code for Digital Clock

Given below code is Simple Digital Clock. It accepts one input as 50 MHz clock and gives three output as Hour, Minute and Second. This code converts internally 50 MHz into 1 Hz Clock Frequency. In this code first process converts frequency from 50 MHz to 1 Hz. in the second process at every clock event second value will increment but up to 59 and then again zero. Same way Minute value will also increment after second value will reach to 59, but up to 59. Hour value will increment when minute value reaches to 59 and goes up to 23 and again goes to zero. In the last integer values of ss, mm and hr are converted into standard logic vector and assign to Second, Minute and Hour respectively. If you want to display this clock on your 7 segment or LCD display then you have write another code that accepts these inputs and generates equivalent output to be displayed.

VHDL Code for Bitonic Sorter

Bitonic Sorter is one kind of Sorting Algorithm. This algorithm invented by Ken Batcher. You can find more detail about this algorithm over here.

Bitonic Sorter

VHDL Code for Generation of 1 KHz and 1 Hz Frequency from 100 MHz Frequency

Given below VHDL code will generate 1 kHz and 1 Hz frequency at the same time. This design takes 100 MHz as a input frequency. For this we need counter with different values and that will generate above frequencies. There is a simple formula to find this count value and it is given below.

Count Value = (Input Frequency) / (2 * Output Frequency).

In our case Count Value for 1 kHz is (100 * 10^6) / (2 * 1 * 10^3) = 50,000. After 50,000 count, level of msClk will change.

and for 1 Hz is (100 * 10^6) / (2 * 1) = 5,00,00,000.

Name of Pins	Direction	Data Width
sysClk	Input	1
msClk	Output	1
secClk	Output	1

VHDL Code for Debouncer Circuit

The debouncer circuit is useful when we specially use push button switches in our design. This design code will generate high pulse for 1 millisecond after press and goes back to low. If you want to input a manual switch signal into a digital circuit you'll need to debounce the signal so a single press doesn't appear like multiple presses. Pin description is given below.

Name of Pins	Direction	Data Width
msClk	Input	1
pb	Input	1
debouncedPb	Output	1