Test Bench for 8-bit Barrel Shifter in VHDL

Find out Design Code Here.

library ieee;
use ieee.std_logic_1164.all;

entity barrel_shifter_tst is

end barrel_shifter_tst;


architecture beh of barrel_shifter_tst is

    component barrel_shifter

    port (
    d_in        : in  std_logic_vector(7 downto 0);   -- input vector
    d_out       : out std_logic_vector(7 downto 0);   -- shifted output
    shift_lt_rt : in  std_logic;                      -- 0=>left_operation 1=>right_operation
    shift_by    : in  std_logic_vector(2 downto 0);   -- 000=> parallel load other=>shift amount
    clk         : in  std_logic;                      -- clock signal
    rst_a       : in  std_logic);                     -- reset signal

 
  end component;
 
signal rst_a_s : std_logic;
signal shift_lt_rt_s: std_logic;
signal shift_by_s : std_logic_vector(2 downto 0);
signal d_out_s,d_in_s : std_logic_vector(7 downto 0);
signal clk_s : std_logic := '1';          -- clk signal

begin  -- arch

  u1 : barrel_shifter port map (
  rst_a      => rst_a_s,
  clk        => clk_s,
  shift_lt_rt   => shift_lt_rt_s,
  d_in       => d_in_s,
  shift_by   => shift_by_s,
  d_out     => d_out_s);


  clockk: process
  begin  -- process clockk
    clk_s <= '1';
    wait for 50 ns;

   clk_s <= '0';
    wait for 50 ns;
  end process clockk;

  tst: process
  begin  -- process tst
    rst_a_s <= '1';
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "001";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "010";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "001";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "010";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "101";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '0';
    shift_by_s<= "111";
    d_in_s <= "11001101";
    wait for 100 ns;

    rst_a_s <= '0';
    shift_lt_rt_s<= '1';
    shift_by_s<= "011";
    d_in_s <= "11001101";
    wait for 100 ns;
  end process tst;

end beh;