VHDL Code for 4-bit Up-Down Counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_down_counter is

  port(clk, rst_a, mode : in std_logic;  --mode=1 up counting, mode=0 down counting
        q : out std_logic_vector(3 downto 0));

end up_down_counter;

architecture archi of up_down_counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
          if (mode='1') then
            tmp <= tmp + 1;
          else
            tmp <= tmp - 1;
          end if;
        end if;
    end process;
    q <= tmp;
end archi;