VHDL Code for 16x9 True Dual Port Memory

Name of the Pin	Direction	Width	Description
address1	Input	4	Input address1 i.e. address bus1
address2	Input	4	Input address2 i.e. address bus2
we1	Input	1	If 0 write in to memory & if 1 read from memory
we2	Input	1	If 0 write in to memory & if 1 read from memory
data1	Input	9	input data1
data2	Input	9	input data2
data_out1	output	9	output data1
data_out2	output	9	output data2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity dual_port_ram is

  port (
    clk            : in std_logic;      -- clk is the clock input.

    ce_l_1, ce_l_2 : in std_logic;  -- ce_l_1, ce_l_2 is the chip enable of port 1 and port 2.

    oe_l_1, oe_l_2 : in std_logic;  -- oe_l_1, oe_l_2 is active low output enable of port 1 and port 2.

    r_w_1, r_w_2   : in std_logic;  -- r_w_1, r_w_2 is read/write signal of port 1 and port 2.

    data_1, data_2 : inout std_logic_vector(8 downto 0);  -- data_1 and data_2 is the data input & output from the memory.

    addr1          : in std_logic_vector(3 downto 0);  -- addr1 is the address for port 1
    addr2          : in std_logic_vector(3 downto 0));  -- addr_2 is the address input for port 2.

end dual_port_ram;

architecture dp_ram of dual_port_ram is

  signal cntrl_1_p1, cntrl_2_p1, cntrl_1_p2, cntrl_2_p2 : std_logic;  -- cntrl_1_p1, cntrl_2_p1, cntrl_1_p2, cntrl_2_p2 are used to generate control signals for reading or writing into memory.

  type mem is array (15 downto 0) of std_logic_vector(8 downto 0);  -- mem is used to define memory.

  shared variable memory : mem;         -- memory is used to define memory.

begin  -- dp_ram

  cntrl_1_p1 <= not((not ce_l_1) and (not r_w_1)); -- control signal for read/write operation for port 1.

  cntrl_2_p1 <= not((not ce_l_1) and (not oe_l_1)); -- control signal for output enable for port 1.

  cntrl_1_p2 <= not((not ce_l_2) and (not r_w_2)); -- control signal for read/write operation for port 2.

  cntrl_2_p2 <= not((not ce_l_2) and (not oe_l_2)); -- control signal for output enable for port 2.

  ----------------------------------------------
  -- purpose: It is used to access port 1.
  -- type   : sequential
  -- inputs : clk, ce_l_1, oe_l_1, r_w_1, data_1
  -- outputs: data_1
  ----------------------------------------------
  port1: process (clk)
  begin  -- process port1
    if clk'event and clk = '1' then  -- rising clock edge
      if cntrl_1_p1 = '0' and cntrl_2_p1 = '1' then  -- Write Operation.
        memory(conv_integer(addr1)) := data_1;
      elsif cntrl_1_p1 = '1' and cntrl_2_p1 = '0' then  -- Read Operation.
        data_1 <= memory(conv_integer(addr1));
      else
        data_1 <= "ZZZZZZZZZ";
      end if;
    end if;
  end process port1;


  -------------------------------------------------------
  -- purpose: It is used to accesss port 2.
  -- type   : sequential
  -- inputs : clk, cs_l_2, oe_l_2, addr_2, data_2, r_w_2
  -- outputs: data_2
  -------------------------------------------------------
  port2: process (clk)
  begin  -- process port2
    if clk'event and clk = '1' then  -- rising clock edge
      if cntrl_1_p2 = '0' and cntrl_2_p2 = '1' then  -- Write Operation.
        memory(conv_integer(addr2)) := data_2;
      elsif cntrl_1_p2 = '1' and cntrl_2_p2 = '0' then  -- Read Operation.
        data_2 <= memory(conv_integer(addr2));
      else
        data_2 <= "ZZZZZZZZZ";
      end if;
    end if;
  end process port2;

end dp_ram