Verilog Code for D-Latch

S.No:	Name	Direction	Width	Remark
1	D_in	IN	1	Input
2	Enb	IN	1	Synchronous Enable Input
3	Q	OUT	1	Output
4	Q_bar	OUT	1	Output

module d_latch(q, q_bar, d_in, enb);
   output q,q_bar;
   input  d_in;
   input  enb;

   nand g1 (s, d_in, enb),
   g2 (r, d_bar, enb);
   not g3 (d_bar,d_in);
   nand g4 (q, s, q_bar);
   nand g5 (q_bar, r, q);

endmodule