Handshakes, FIFOs, and the Magic of Gray Code in Multi-Bit CDC

In our last post, we tackled the silent silicon killer known as Metastability and explored how the trusty 2-Flop Synchronizer safely passes a single control bit across different clock domains. 

But what happens when you need to send an entire 32-bit data bus from a 1GHz processor to a 400MHz memory controller? 

Spoiler alert: You cannot just slap thirty-two 2-Flop Synchronizers in parallel and call it a day. Today, we are diving into the practical magic of Asynchronous FIFOs and why a mathematical curiosity from the 1940s called Gray Code is the only thing keeping modern microchips from collapsing into chaos.

The Multi-Bit Disaster: Why 2-Flop Synchronizers Fail on Buses

Imagine trying to pass a binary counter value of 3 (011 in binary) changing to 4 (100 in binary) across a clock domain using parallel synchronizers. Notice that three separate bits are changing simultaneously to make that jump.

In the physical world of silicon, perfectly simultaneous events do not exist. Microscopic variations in wire routing, parasitic capacitance, and temperature mean those three bits will arrive at the destination flip-flops at slightly different picoseconds. This is called Bus Skew.

If the destination clock ticks exactly while those bits are transitioning, some flip-flops will capture the old value, some will capture the new value, and some will go metastable. Your destination domain might stitch those bits together and read 7 (111) or 0 (000). This generates a garbage memory address that will instantly crash your system.

To fix this, we have two primary weapons in RTL design: Handshaking and Asynchronous FIFOs.

Understanding Metastability and Clock Domain Crossing (CDC)

If you’ve taken a digital logic class, you know the golden rule: everything happens on the clock edge. Your flip-flops read the input, store the state, and pass it to the next logic gate in perfect synchronization.

But what happens when your design has more than one clock?

In modern ASICs and FPGAs, a single chip might have a 1GHz processor, a 400MHz memory controller, and a 50MHz UART interface. When data needs to move between these independent clock domains—a process known as Clock Domain Crossing (CDC)—the perfect synchronization of the classroom goes out the window, and you enter the dangerous territory of Metastability. 

The Setup and Hold Violation 

To understand metastability, we have to look at the physical physics of a flip-flop. For a flip-flop to reliably capture a 1 or a 0, the data signal must be stable for a specific amount of time before the clock edge (Setup Time) and remain stable for a specific amount of time after the clock edge (Hold Time).

When data crosses from Domain A (e.g., 100MHz) to Domain B (e.g., 33MHz), Domain B's clock has no idea when Domain A's data is changing. It is almost guaranteed that eventually, Domain B's clock will tick exactly at the moment Domain A's data is transitioning between a 0 and a 1.

This violates setup and hold times, causing the flip-flop to go metastable. 

The Ultimate Base Converter: Bridging the Gap Between Humans and Hardware

Base Converter

Decimal (Base 10)

Invalid decimal character

Binary (Base 2)

Invalid binary character (Use 0 or 1)

Octal (Base 8)

Invalid octal character (Use 0-7)

Hexadecimal (Base 16)

Invalid hex character (Use 0-9, A-F)

Verilog code to count number of 1's and 0's in 32-bit data input

There are many places where we need to check how many 0's or 1's are present in incoming data. It can be packet inspection or these counting further can be used for different purposes. This Verilog code is designed to efficiently count the occurrences of both '1' and '0' bits within a 32-bit input data. The primary objective of this module is to provide an accurate count of the number of '1's and '0's present in the input data simultaneously. Module takes 32-bit input data with valid bit. There are also clock and reset signals. Module has two output count vlaues, one for number of 1's and another one for number of 0's, and one valid signal. 32-bit input data is fed to the function only on valid_input and function will return number of 1's in the 32-bit data. This value will be subtracted from 32 and it will give us number of 0's present in the data. Both output values are true only when output_valid signal is high.

Rising and Falling Edge Detector using Verilog

 In the real word, there might be many scenario that we need to detect rising edge or falling edge of the signal. If rising/falling edge happens on particular signal, then design can perform certain task. This rising or falling edge can be detected using following code. This code is done in Verilog language. In given below example code, clock clk, input signal sig_a, output rising edge signal ris_a and falling edge signal fal_a are defined. Both ris_a and fal_a are high for one clock cycle when circuit detects rising or falling edge on the sig_a respectively.