Design a Constant Divider using VHDL Coding.

Constant Divider circuit accepts an input of 8 bit wide and divides it by constant value 53. The divider circuit will generate two output values as remainder and quotient. As we know that the division operator is not synthesizable, so division is done by repetitive subtraction method. As an example of input is 108, the remainder is 2 and quotient is 2 while if input is 20, remainder is 20 and quotient is 0. In this design Inp is input with 8 bit long, Remi and Quo are two output signals with 6-bit and 3-bit long respectively. Here bit lengths of Remi and Quo are decided as per getting maximum value. Divider is constant which is 8 bit long and value is "00110101". Binary value of 53 is "00110101".

Design 4-bit Linear Feedback Shift Register (LFSR) using VHDL Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. It is used for State Encoding. It is also used to generate random numbers. Find out Verilog code here.

Design 8 bit Ripple Carry Adder using VHDL Coding and Verify using Test Bench

Given below code will generate 8 bit output as sum and 1 bit carry as cout.  it also takes two 8 bit inputs as a and b, and one input carry as cin. This code is implemented in VHDL by structural style. Predefined full adder code is mapped into this ripple carry adder. Full Adder code can be found here. Carry is generated by adding each bit of two inputs and propagated to next bit of inputs. If carry is generated by adding seventh bits and previous carry, then cout bit goes high.

Design Gray Counter using VHDL Coding and Verify with Test Bench

Given below code is about Gray Counter in VHDL. In a gray code only one bit changes at a one time. This design code has two inputs clock and reset signals and one four bit output that will generate gray code. In the first if rst signal is high then output will be zero and as soon as rst will go low, on the rising edge of clk, design will generate four bit gray code and continue to generate at every rising edge of clk signal. This design code can be upgraded and put binary numbers as a input and this design will work as binary to gray code converter. Find out Verilog Code of Gray Counter here.

Design BCD to 7-Segment Decoder using VHDL Code

Given below VHDL code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find out Verilog Code here.

Common Cathode Seven Segment Display

Design Johnson Counter and Test with Test Bench using VHDL Code

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find out Verilog Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

VHDL Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out Verilog Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

Verilog and VHDL Code for Digital Clock

Given below code is Simple Digital Clock. It accepts one input as 50 MHz clock and gives three output as Hour, Minute and Second. This code converts internally 50 MHz into 1 Hz Clock Frequency. In this code first process converts frequency from 50 MHz to 1 Hz. in the second process at every clock event second value will increment but up to 59 and then again zero. Same way Minute value will also increment after second value will reach to 59, but up to 59. Hour value will increment when minute value reaches to 59 and goes up to 23 and again goes to zero. In the last integer values of ss, mm and hr are converted into standard logic vector and assign to Second, Minute and Hour respectively. If you want to display this clock on your 7 segment or LCD display then you have write another code that accepts these inputs and generates equivalent output to be displayed.

VHDL Code for Bitonic Sorter

Bitonic Sorter is one kind of Sorting Algorithm. This algorithm invented by Ken Batcher. You can find more detail about this algorithm over here.

Bitonic Sorter

VHDL Code for Generation of 1 KHz and 1 Hz Frequency from 100 MHz Frequency

Given below VHDL code will generate 1 kHz and 1 Hz frequency at the same time. This design takes 100 MHz as a input frequency. For this we need counter with different values and that will generate above frequencies. There is a simple formula to find this count value and it is given below.

Count Value = (Input Frequency) / (2 * Output Frequency).

In our case Count Value for 1 kHz is (100 * 10^6) / (2 * 1 * 10^3) = 50,000. After 50,000 count, level of msClk will change.

and for 1 Hz is (100 * 10^6) / (2 * 1) = 5,00,00,000.

Name of Pins	Direction	Data Width
sysClk	Input	1
msClk	Output	1
secClk	Output	1

VHDL Code for Debouncer Circuit

The debouncer circuit is useful when we specially use push button switches in our design. This design code will generate high pulse for 1 millisecond after press and goes back to low. If you want to input a manual switch signal into a digital circuit you'll need to debounce the signal so a single press doesn't appear like multiple presses. Pin description is given below.

Name of Pins	Direction	Data Width
msClk	Input	1
pb	Input	1
debouncedPb	Output	1

VHDL Code of (7,4) Hamming Code Encoder

Name of Pins	Direction	Width
Datain	Input	4
Hamout	Output	7

Hamming code is useful in Error Correction in Linear Block Code. This code will encode four bits of data and generate seven bits of code by adding three bits as parity bits. It was introduced by Richard W. Hamming. This algorithm can detect one and two bit error and can correct one bit error. Given below code will generate (7,4) Systematic Hamming Encoder. This encoder will use Least Significant 4 bits as data inputs and Most 3 significant bits as a parity bits.

Parity bits equations are given below

p0 = datain(0) xor datain(1) xor datain(3)

p1 = datain(0) xor datain(2) xor datain(3)

p2 = datain(1) xor datain(2) xor datain(3)

VHDL Code for Bidirectional Bus

Here I have given a block diagram of Bidirectional Bus. This bus takes input from Data_in and gives output from Bi_Data when OE signal is high. In the same way when OE signal is low then it takes input from Bi_Data and gives output from Data_Out. Below I have mentioned input output into table.

VHDL Code for Round Robin Arbiter with Fixed Time Slices

S.No.	Name	Direction	Width	Remark
1	Rst	Input	1	Reset signal
2	Clk	Input	1	Clock signal
3	Req	Input	4	Request for user1 ,user2,user3,user4
4	Gnt	Output	4	four grant signal to the Users

Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system. As the term is generally used, time slices are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. Find out Round Robin Arbiter with variable time slice here.

VHDL Code for Fixed Priority Arbiter

S.No.	Name	Direction	Width	Remark
1	Rst	Input	1	Reset signal
2	Clk	Input	1	Clock signal
3	Req	Input	4	Request for user1 ,user2,user3,user4
4	Gnt	Output	4	four grant signal to the Users

The above design is a Priority Resolver circuit which gives priority to the requests of that user which was given grant the most earlier. In other way the user which was given grant most recently is given least priority. If the two requests have ,by chance, conflict in getting the grant, they will be issued the grant signal according to the following sequence:

req0     >          req1     >          req 3    >          req4

VHDL Code for Synchronous FIFO

Sr. No.	Name of the Pin	Direction	Width	Description
1	Rst_a	Input	1	Reset Input
2	Clk	Input	1	Clock Input
3	we	Input	1	when high write into fifo and when low read from memory
5	Data_in	Input	8	Data Input
6	Data_out	Output	8	Data output
7	Full	Output	1	Fifo status 1 if fifo is full
8	Empty	Output	1	Fifo status 1 if fifo is empty

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity fifo is
  
  generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 8);         -- data_width

  port (
    data_in  : in  std_logic_vector(7 downto 0);  -- data
    data_out : out std_logic_vector(7 downto 0);  -- data_out
    clk      : in  std_logic;           -- clock signal
    rst      : in  std_logic;           -- reset signal
    we       : in  std_logic;           --write enable signal
    full     : out  std_logic;           -- full signal
    empty    : out std_logic);          -- empty signal

end fifo;

architecture beh of fifo is
constant depth : integer := 2**addr_width;  -- depth of ram

signal rd_point : std_logic_vector(addr_width-1 downto 0) := "0000";  -- read pointer

signal wr_point : std_logic_vector(addr_width-1 downto 0) := "0000";  -- write pointer

signal status : std_logic_vector(addr_width-1 downto 0) := "0000";  -- status pointer

signal ram_out : std_logic_vector(data_width-1 downto 0);  -- data out from ram

signal full_s,empty_s : std_logic;


component dual_port_ram 
generic (
    addr_width : integer := 4;          -- address width
    data_width : integer := 8);         -- data_width

 port (
    address1  : in  std_logic_vector(addr_width-1 downto 0);  -- address for port1
    data1     : in  std_logic_vector(data_width-1 downto 0);  -- data for port1
    we1       : in  std_logic;                     -- write enable for port1
    address2  : in  std_logic_vector(addr_width-1 downto 0);  -- address for port2
    data2     : in  std_logic_vector(data_width-1 downto 0);  -- data for port2
    we2       : in  std_logic;                     -- write enable for port 2
    data_out1 : out std_logic_vector(data_width-1 downto 0);  -- data_out for port 1
    data_out2 : out std_logic_vector(data_width-1 downto 0);  -- data out for port 2
    clk       : in  std_logic                     -- clock signal
   );                    -- reset signal

end component;
  
begin  -- beh


  full_s <= '1' when (status=(depth-1)) else '0';
  empty_s <= '1' when (status="0000") else '0';
  full<=full_s;
  empty<=empty_s;

  read_pointer: process (clk,rst)
  begin  -- process read_pointer
    if rst='1' then
      rd_point<="0000";
    elsif rising_edge(clk) then
      if we='0' then
        rd_point<=rd_point+'1';
      end if;
    end if;
  end process read_pointer;


  write_pointer: process (clk,rst)
  begin  -- process write_pointer
    if rst='1' then
      wr_point<="0000";
    elsif rising_edge(clk) then
      if we='1' then
        wr_point<=wr_point+'1';
      end if;
    end if;
  end process write_pointer;


  status_count: process (clk,rst)
  begin  -- process status
    if rst='1' then
      status<="0000";
    elsif rising_edge(clk) then
      if we='1' and status /= "1111" then
        status<=status+'1';
      elsif we='0' and status /= "0000" then
        status<=status-'1';        
      end if;
    end if;
  end process status_count;

assertions : process (we,full_s,empty_s)
begin
    if (full_s='1') then
       assert we='0' report "ram is full & you are overwritting to ram" severity error;
  elsif (empty_s='1') then
       assert we='1' report "ram is empty & you are reading the previos data from ram" severity error; 
  end if;
end process assertions;



  u1: dual_port_ram   
  generic map (
    addr_width => 4,          -- address width
    data_width => 8)         -- data_width

  port map (
      address1  => wr_point,
      data1     => data_in,
      we1       => we,
      clk       => clk,
      address2  => rd_point,
      data2     => data_in,
      data_out2 => data_out,
      data_out1 => open,
      we2       => we
      );
  

end beh;