VHDL Code for Fixed Priority Arbiter

S.No.	Name	Direction	Width	Remark
1	Rst	Input	1	Reset signal
2	Clk	Input	1	Clock signal
3	Req	Input	4	Request for user1 ,user2,user3,user4
4	Gnt	Output	4	four grant signal to the Users

The above design is a Priority Resolver circuit which gives priority to the requests of that user which was given grant the most earlier. In other way the user which was given grant most recently is given least priority. If the two requests have ,by chance, conflict in getting the grant, they will be issued the grant signal according to the following sequence:

req0     >          req1     >          req 3    >          req4

library ieee;
use ieee.std_logic_1164.all;

entity fixed_priority is

  port (
    gnt : out std_logic_vector(3 downto 0);  -- Output grant signal
    req : in std_logic_vector(3 downto 0);  -- Input request signal
    clk : in std_logic;                     -- system clock
    rst : in std_logic);                    -- async reset

end fixed_priority;

architecture ARCH of fixed_priority is

  signal tmp_gnt : std_logic_vector(3 downto 0) := "0000";  -- tmporary grant signal

begin  -- ARCH

  -- purpose: fixin the priority
  -- type   : combinational
  -- inputs : req
  -- outputs: gnt

prio: process (req,rst)
  begin  -- process prio
    if(rst='1') then
      tmp_gnt<="0000";
    else
    if req="0000" then
        tmp_gnt<="0000";
 
 elsif req(0)='1' then
      tmp_gnt(0)<='1';
      tmp_gnt(1)<='0';
      tmp_gnt(2)<='0';
      tmp_gnt(3)<='0';

    elsif req(1)='1' then
      tmp_gnt<="0010";

    elsif req(2)='1' then
      tmp_gnt<="0100";

    elsif req(3)='1' then
      tmp_gnt<="1000";
    end if;
  end if;

  end process prio;

  -- purpose: assigning priority
  -- type   : sequential
  -- inputs : clk, rst, req
  -- outputs: gnt

  assign: process (clk, rst)
  begin  -- process assign
    if rst = '1' then                   -- asynchronous reset (active low)
      gnt<="0000";
    elsif clk'event and clk = '1' then  -- rising clock edge
      gnt<=tmp_gnt;
   
    end if;
  end process assign;

  assertion: process (tmp_gnt)
    begin
      if(tmp_gnt="0001") then
        assert false report "Req(0) is granted and have highest priority" severity note;

      elsif(tmp_gnt="0010") then
        assert false report "Req(1) is granted and have 2nd highest priority" severity note;

      elsif(tmp_gnt="0100") then
        assert false report "Req(2) is granted and have 3rd highest priority" severity note;

      elsif(tmp_gnt="1000") then
        assert false report "Req(3) is granted and have lowest priority" severity note;
      end if;

    end process assertion;

end ARCH;