Verilog Code for 8-Bit ALU

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	8	Data Input
2	b	Input	8	Data Input
3	opcode	Input	4	Control Logic for different operation
4	Op	Output	8	Output

There are total three inputs and one output signals. Two inputs a and b are input signals on which operation is going to be performed according to opcode input. a and b are 8 bit wide. opcode is 4 bit wide, so we can do sixteen different operations. The design code is given below. This is simple ALU. 

Design 8x3 Priority Encoder in Verilog Coding and Verify with TestBench

Priority Encoder allocates priority to each input. Design and Test Bench code of 8x3 Priority Encoder is given below. Output are set according to priorities of inputs. So if input with higher priority is present then inputs with lower priorities are ignored and generates output according to highest priority input.

S. No.	Name	Direction	Width	Remark
1.	D_in	IN	8 bit	Input lines
3.	D_out	OUT	3 bit	Output lines

Verilog Code for 4x16 Decoder

Sr. No.	Name of the Pin	Direction	Width	Description
1	D_in	Input	4	Input to be decoded
2	D_out	Output	16	Decoded output

module decoder_4x16 (d_out, d_in);

   output [15:0] d_out;
   input [3:0]   d_in;
   parameter tmp = 16'b0000_0000_0000_0001;

assign d_out = (d_in == 4'b0000) ? tmp   :
               (d_in == 4'b0001) ? tmp<<1:
               (d_in == 4'b0010) ? tmp<<2:
               (d_in == 4'b0011) ? tmp<<3:
               (d_in == 4'b0100) ? tmp<<4:
               (d_in == 4'b0101) ? tmp<<5:
               (d_in == 4'b0110) ? tmp<<6:
               (d_in == 4'b0111) ? tmp<<7:
               (d_in == 4'b1000) ? tmp<<8:
               (d_in == 4'b1001) ? tmp<<9:
               (d_in == 4'b1010) ? tmp<<10:
               (d_in == 4'b1011) ? tmp<<11:
               (d_in == 4'b1100) ? tmp<<12:
               (d_in == 4'b1101) ? tmp<<13:
               (d_in == 4'b1110) ? tmp<<14:
               (d_in == 4'b1111) ? tmp<<15: 16'bxxxx_xxxx_xxxx_xxxx;

endmodule

Verilog Code for D-Latch

S.No:	Name	Direction	Width	Remark
1	D_in	IN	1	Input
2	Enb	IN	1	Synchronous Enable Input
3	Q	OUT	1	Output
4	Q_bar	OUT	1	Output

module d_latch(q, q_bar, d_in, enb);
   output q,q_bar;
   input  d_in;
   input  enb;

   nand g1 (s, d_in, enb),
   g2 (r, d_bar, enb);
   not g3 (d_bar,d_in);
   nand g4 (q, s, q_bar);
   nand g5 (q_bar, r, q);

endmodule

Verilog Code for 4-Bit Full Adder using 1-Bit Adder

Sr. No.	Name of the Pin	Direction	Width	Description
1	a	Input	4	Data Input
2	b	Input	4	Data Input
3	cin	inout	1	Input carry
4	Sum	Output	4	Summation
5	Cout	Output	1	Carry

Verilog Code for 1-bit Adder

module full_adder(sum,cout,a,b,cin);
   output sum;
   output cout;
   input  a,b,cin;
 
   assign{cout,sum}=a+b+cin;
endmodule

VHDL Code for Round Robin Arbiter with Fixed Time Slices

S.No.	Name	Direction	Width	Remark
1	Rst	Input	1	Reset signal
2	Clk	Input	1	Clock signal
3	Req	Input	4	Request for user1 ,user2,user3,user4
4	Gnt	Output	4	four grant signal to the Users

Round-robin (RR) is one of the simplest scheduling algorithms for processes in an operating system. As the term is generally used, time slices are assigned to each process in equal portions and in circular order, handling all processes without priority (also known as cyclic executive). Round-robin scheduling is simple, easy to implement, and starvation-free. Round-robin scheduling can also be applied to other scheduling problems, such as data packet scheduling in computer networks. Find out Round Robin Arbiter with variable time slice here.

VHDL Code for Fixed Priority Arbiter

S.No.	Name	Direction	Width	Remark
1	Rst	Input	1	Reset signal
2	Clk	Input	1	Clock signal
3	Req	Input	4	Request for user1 ,user2,user3,user4
4	Gnt	Output	4	four grant signal to the Users

The above design is a Priority Resolver circuit which gives priority to the requests of that user which was given grant the most earlier. In other way the user which was given grant most recently is given least priority. If the two requests have ,by chance, conflict in getting the grant, they will be issued the grant signal according to the following sequence:

req0     >          req1     >          req 3    >          req4