VHDL Code for Generation of 1 KHz and 1 Hz Frequency from 100 MHz Frequency

Given below VHDL code will generate 1 kHz and 1 Hz frequency at the same time. This design takes 100 MHz as a input frequency. For this we need counter with different values and that will generate above frequencies. There is a simple formula to find this count value and it is given below.

Count Value = (Input Frequency) / (2 * Output Frequency).

In our case Count Value for 1 kHz is (100 * 10^6) / (2 * 1 * 10^3) = 50,000. After 50,000 count, level of msClk will change.

and for 1 Hz is (100 * 10^6) / (2 * 1) = 5,00,00,000.

Name of Pins	Direction	Data Width
sysClk	Input	1
msClk	Output	1
secClk	Output	1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clockGenerator is 
	port( 
		sysClk:	in std_logic;--100Mhz clock
		msClk :	out std_logic;
		secClk: out std_logic);
end clockGenerator;

architecture Behavioral of clockGenerator is 
begin 
	process (sysClk)
		variable cnt: integer range 0 to 100000 := 0;
		variable mscnt:	integer range 0 to 1000 := 0;
	begin
		if(sysClk'event and sysClk='1')then 
			cnt:=cnt+1;
					
			--generates msClk	
			if (cnt=50000) then --half a millisecond	 
				msClk<='1';
			elsif (cnt=100000) then --a full millisecond
				msClk <= '0';
				cnt:= 0;
				msCnt:= msCnt + 1;
			end if;
				
			--generates secClk
			if (msCnt = 500)then --half a second
				secClk<='1';
			elsif (mscnt = 1000) then --a full second
				secClk <='0';
				mscnt:=0;
			end if;
			
		end if;
	end process; 
end Behavioral;