A Brief Overview Of Data Type in VHDL.

VHDL is strongly typed language and it supports a variety of Data Types and Operators. Users can also define their own data types and operators in user defined packages. There are three basic classes to define data objects in VHDL language.

• Signal : It represents interconnections that connect components and parts.
• Variable : It is used for local storage within process.
• Constant : It is used to declare a fixed value.

The data object can be a scalar or an array (one dimensional as well as multi dimensional).

• Bit Data Type : It is used to represent value of a digital system. '0' and '1' are allowed assign bit data type.
• Bit vector is expressed as a string of bit literals enclosed in double quotes.
• signal valid : bit := '1'
• signal valid : bit_vector := "0011"
• signal valid : bit_vector := X"7CEF"
• Boolean Data Type : It represents true or false value. Values allowed are true(TRUE,True) and false(FALSE,False).
• signal busactive : boolean := true;
• Character Data Type : The package STANDARD predefines a set of character literals. Character literals are enclosed in single quotes. Ex. 'a', 'A', '1', '!' An array of character literals is enclosed in double quotes. Ex "Warning : timing violation". This data type is not synthesizable.
• Integer Data Type : It defines a value with integer. Values are called integer literals. Thary can be either positive or negative value. Exponents have to be integers. By default integer size is 32 bits. Integer range is -2^31 to [2^(31) - 1].
• signal round : integer := 47E23; 
• constant state : integer := -63;
• Real Data Type : It defines a value with real numbers. They can be either positive or negative. Exponents have to be integers.
• signal a : real := -1.0E10;
• signal b : real := 1.6;
• Physical Data Type : It is used to represent physical quantities like distance, current, time etc. Values are called physical literals. The only predefined physical type time is defined in package STANDARD. Predefined function "now" returns the current simulation time, which is kind of physical data type. The range of a physical type is always in terms of its base unit. User can define their own physical types. This data type is not synthesizable.
• constant clock_period : time := 10 ns;
• STD_LOGIC Type : This data type is defined in std_logic_1164 package of IEEE library. It defines a number of the states for a digital signal which helps in simulation and debugging. std_logic contains nine different values..
• 'U' - Uninitialized
• 'X' - Forcing Unknown
• '0' - Forcing zero
• '1' - Forcing one
• 'Z' - High Impedance
• 'W' - Weak Unknown
• 'L' - Weak zero
• 'H' - Weak one
• '-' - Don't Care
• signal ip : std_logic := '1';
• signal bus : std_logic_vector(3 downto 0) := "1100";
• Enumerated Type : This data type defines a set of user defined values consisting of identifiers and characters. The enumerated literal are listed in the ascending order. Actual numeric value can be assigned to the literals during compile time. Enumerated type allows us to use symbolic values instead of numeric values. Boolean, Bit, Character are some of the predefined enumerated data type. This is declared as given below
• Type enumerated_name is (enumerated literal1, literal2,literal3,...);
• type color is (Red,Blue,Pink);
• type state is (idle, load, start, stop, store);
• Subtype Data Type : It allows for user to use with a range constraint. Subtypes are compatible with their base type. We may include entire range of base type. Assignments those are out of the subtype range are illegal. Range violation detected at only at run time.
• SUBTYPE name IS base_type RANGE user_range;
• SUBTYPE digit IS integer RANGE 0 to 9;
• SUBTYPE nanosec IS time RANGE 0 ns to 1us;
• Composite Data Type : There are two composite type (1) Array and (2) Records
• Array : It contains many elements of same type. Range may be unconstrained in declaration and it can be constrained when array is used. Arrays can be uni or multi dimensional.
• type array_name is array (index range) of element_type;
• type byte is array (7 downto 0) of std_logic;
• type word is array (integer range <>) of std_logic;
• type array_name is array (index_range, index_range) of element_type;
• type memory is array (3 downto 0, 7 downto 0) of bit; -- 4x8 memory
• Synthesis tools do not accept multidimensional array. So one can declare two uni-dimensional arrays.
• type byte is array (7 downto 0) of std_logic;
  type mem is array (3 downto 0) of byte;
• Record : It is used to group elements of different data types into a single object. 
• type my_type is
  record
     is_valid : boolean;
     value : std_logic_vectr(7 downto 0);
     when_updated : time;
  end record;
  signal my_element : my_type;
• my_element <= (is_valid => true; value => "00110011"; when_updated => 10 ns);
• my_element.value <= "10101100";