VHDL has wide range of Operators, which can be grouped into following
- Logical Operators
- Relational Operators
- Shift Operators.
- Miscellaneous Operators
- Logical Operators
- These operators can be applied on variable and signals of std_logic, bit and boolean data types.
- These can't applied to any user defined data types.
- There are seven logical operators : And, Or, Nand, Nor, Xor, Xnor and Nota = "0011", b="1010"y_and <= a and b; so y_and will be "0010"y_or <= a or b; then y_or will be "1001"y_nand <= a nand b; then y_nand will be "1101"y_nor <= a nor b; then y_nor will be "0110"y_xor <= a xor b; then y_xor will be "1001"y_xnor <= a xnor b; then y_xnor will be "0110"y_not <= not a; then y_not will be "1100"
- Relational Operators
- These operators are used in expression when it is necessary to compare the values of objects.
- Values returned by such expression is always Boolean type. It returns True if condition in given relation is met otherwise False is returned.
- There are six relational operators. equal to(=), not equal to(/=), less than(<), less than or equal to(<=), greater than(>), greater than or equal to(>=).a = "0101", b = "1010"a = b; --> Falsea /= b; --> Truea < b; --> Truea <= b; --> Truea > b; --> Falsea >= b; --> False
- Shift Operators
- There are total three types of shift operators
- Logical.
- Arithmetic.
- Rotate.
- Find out more about Shift Operators here.
- Miscellaneous Operators
- There are Addition(+), Subtraction(-), Concatenation(&), Multiplication(*), Division(/), Reminder(rem), Modulus(mod), Absolute(abs) and Exponentiation(**) operators used in VHDL.
- a = "1010", b = "0011"y_addition <= a + b; then y_addition will be "1101"y_sub <= a - b; then y_sub will be "0111"y_con <= a & b; then y_con will be "10100011". Join a and b.y_mul <= a * b; then y_mul will be "00011110"y_div <= a / b; then y_div will be "0011"c1 <= 3, d1 <= 8, c2 <= -3, d2 <= -8y_exp <= c1 ** d1; then y_exp will be 6561.y_rem <= d1 rem c1, then y_rem will be 5.y_rem <= d1 rem c2, then y_rem will be 5.y_rem <= d2 rem c1, then y_rem will be -5.y_rem <= d2 rem c2, then y_rem will be -5.y_mod <= d1 mod c1, then y_rem will be 5.y_mod <= d1 mod c2, then y_rem will be -5.y_mod <= d2 mod c1, then y_rem will be 5.y_mod <= d2 mod c2, then y_rem will be -5.
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