Verilog and VHDL Code for Digital Clock

Given below code is Simple Digital Clock. It accepts one input as 50 MHz clock and gives three output as Hour, Minute and Second. This code converts internally 50 MHz into 1 Hz Clock Frequency. In this code first process converts frequency from 50 MHz to 1 Hz. in the second process at every clock event second value will increment but up to 59 and then again zero. Same way Minute value will also increment after second value will reach to 59, but up to 59. Hour value will increment when minute value reaches to 59 and goes up to 23 and again goes to zero. In the last integer values of ss, mm and hr are converted into standard logic vector and assign to Second, Minute and Hour respectively. If you want to display this clock on your 7 segment or LCD display then you have write another code that accepts these inputs and generates equivalent output to be displayed.

-------------------------------VHDL Code-----------------------------

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity digital_clock is
port(clk_50 : in std_logic;
  second : out std_logic_vector(5 downto 0);
  minute : out std_logic_vector(5 downto 0);
  hour : out std_logic_vector(4 downto 0));
end entity;

architecture beh of digital_clock is
signal ss, mm : integer range 0 to 59;
signal hr : integer range 0 to 23;
signal count : integer := 1;
signal clk1 : std_logic := '1';

begin
-- 1 Hz clock Generation from 50 MHz clock.
clock_generation : process (clk_50)
 begin
  if (rising_edge(clk_50)) then
   count <= count + 1;
   if (count = 25000000) then
    clk1 <= not clk1;
    count <= 1;
   end if;
  end if;
 end process;

-- Functionality of Digital Clock.
digital : process (clk1)
 begin
  if (rising_edge(clk1)) then
   if (ss = 59) then
    ss <= 0;
    if (mm = 59) then
     mm <= 0;
     if (hr = 23) then
      hr <= 0;
     else
      hr <= hr + 1;
     end if;
    else
     mm <= mm + 1;
    end if;
   else
    ss <= ss + 1;
   end if;
  end if;
 end process;

--Converts Integer Values into Standard Logic Vector. 
second <= conv_std_logic_vector(ss,6);
minute <= conv_std_logic_vector(mm,6);
hour <= conv_std_logic_vector(hr,5);

end beh;

-------------------------Verilog Code-------------------------

module digital_clock(clk_50,second,minute,hour);
 output reg [5:0] second, minute;
 output reg [4:0] hour;
 input clk_50;

 reg [24:0] count = 1;
 reg clk1 = 0;
 
always @(posedge clk_50)
 begin
  if(count == 25'd25000000) begin
   clk1 <= ~ clk1;
   count <= 25'd1;
  end else begin
   count <= count + 25'd1;
  end
 end
 
always @(posedge clk1)
 begin
  if (second == 6'd59) begin
   second <= 6'd0;
   if (minute == 6'd59) begin
    minute <= 6'd0;
    if (hour == 5'd23) begin
     hour <= 5'd0;
    end
    else begin
     hour <= hour + 5'd1;
    end
   end
   else begin
    minute <= minute + 6'd1;
   end
  end
  else begin
   second <= second + 6'd1;
  end
 end

endmodule