Quick Overview To Start Coding into Verilog

• Verilog is very popular Hardware Description language. It was introduced by Gateway Design Automation in 1984. In 1989, Cadence Design Systems purchased and put into public domain in 1990. In 1993, OVI enhanced the verilog language but that was not well accepted. IEEE standardized the Verilog HDL(IEEE 1364-1995) in 1995. In 2001, extension to verilog-95 submitted to IEEE and accepted verilog IEEE std 1364-2001. The revision of the language is also done in 2002 and 2005.
• Verilog is case sensitive. Key word are defined in lower case. Most of the syntax is adopted from "C" language. There is no concept of package like in VHDL.
• In Verilog, comments can be specified in two ways(exactly same way as in C/C++).
• Single line comment :It begins with double slashes(//).
• Block comment : It enclose comments between the characters /* and *.
• a = c + d ; // this is an example of single line comment.
• b = a + d ; /* This is an example of block comment*/
• In Verilog, Identifiers are user defined word for variables, function names, module names, block names and instance names. It may contain letters(A-Z, a-z), digits(0-9), _ and $. Identifier must begin with a letter or underscore(not with a number or $). Identifiers are case sensitive in verilog.
• Ex. Adder, shift_by_8bit, _CPA_.
• Keyword are special identifiers reserved to define language constructs. These must be in lower case.
• Ex always, initial, module.
• There are two types of number specification in verilog. (1)Sized Numbers and (2) Unsized Numbers.
• Syntax '
• Size is decimal number which specifies the number of bits present in the number.
• Base format
• 'd or 'D for decimal
• 'h or 'H for hexadecimal
• 'b or 'B for binary
• 'o or 'O for octal
• 567 // decimal number by default
• 3'h345 // 3 bit hexadecimal number.
• 'O121 // octal number
• -8'd5 // 2's complement of 5
• 16'h23x / 16 bit hexadecimal numbers, with 8 LSBs are unknown.
• 8'b1100_0011_1010_1011 // "_" is allowed anywhere except in the begging.
• A module is the principal design unit in Verilog. It describes both designer interface to other designs, and its functional composition. All the declaration used in the design must be defined locally with in the module. Functional composition is the description of structure using primitive, data flow assignments and sequential construct. A module can be instantiated as a component in another module. Port list gives details of ports through which module communicates with the external module. Ports can be input, output or input(bi-directional).
• module (port_list);
  input [msb:lsb] input_port_list;
  output [msb:lsb] output_port_list;
  .....statements.....
  endmodule