Design BCD to 7-Segment Decoder using VHDL Code

Given below VHDL code will convert 4 bit BCD into equivalent seven segment number. It will accept 4 bit input and generate seven bit output. One seven segment can show zero to nine digit, so there is 4 bit input. Code is written for Common Cathode seven segment LED.So, LEDs will glow when the input is high. Find out Verilog Code here.

Common Cathode Seven Segment Display

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--bcd to 7 segement decoder
entity seven_seg_decoder is
port(clk: in std_logic;
  bcd: in std_logic_vector (3 downto 0);
  seven_seg: out std_logic_vector (6 downto 0));
end seven_seg_decoder;


architecture beh of seven_seg_decoder is

begin

process(clk, bcd)
begin
 if (clk'event and clk = '1') then
  case bcd is
   when "0000" => seven_seg <= "1111110"; --0
   when "0001" => seven_seg <= "0110000"; --1 
   when "0010" => seven_seg <= "1101101"; --2
   when "0011" => seven_seg <= "1111001"; --3
   when "0100" => seven_seg <= "0110011"; --4
   when "0101" => seven_seg <= "1011011"; --5
   when "0110" => seven_seg <= "1011111"; --6
   when "0111" => seven_seg <= "1110000"; --7 
   when "1000" => seven_seg <= "1111111"; --8
   when "1001" => seven_seg <= "1110011"; --9
   when others => seven_seg <= "0000000"; --no display
  end case;
 end if;
end process;

end beh;

Given design code is synthesized by Xilinx Vivado. RTL view of design is given below. Rom is implemented using LUTs.

RTL view of Design