Verilog Code for Johnson Counter

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find VHDL Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Out	Output	4	Output Signal

module ring_counter(out, clk, rst);
  input clk, rst;
  output reg [3:0] out;
always @(posedge clk, posedge rst)
  begin
 if (rst)
  out = 4’b0000;
 else
  out = {~out[0];out[3:1]};
  end
endmodule