Design Gray Counter using VHDL Coding and Verify with Test Bench

Given below code is about Gray Counter in VHDL. In a gray code only one bit changes at a one time. This design code has two inputs clock and reset signals and one four bit output that will generate gray code. In the first if rst signal is high then output will be zero and as soon as rst will go low, on the rising edge of clk, design will generate four bit gray code and continue to generate at every rising edge of clk signal. This design code can be upgraded and put binary numbers as a input and this design will work as binary to gray code converter. Find out Verilog Code of Gray Counter here.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity gray_counter is
port(clk: in std_logic;
  rst: in std_logic;
  gray_code: out std_logic_vector (3 downto 0));
end gray_counter;

architecture beh of gray_counter is
signal count : std_logic_vector(3 downto 0) := "0000";
begin
 process(clk)
 begin
  if (rst='1') then
   count <= "0000";
  elsif (rising_edge(clk)) then
   count <= count + "0001";
  end if;
 end process;
    gray_code <= count xor ('0' & count(3 downto 1));
end beh;

Above design code is synthesized by Xilinx Vivado and RTL view of the gray counter is shown below.

RTL view of Gray Counter

Test Bench code for above design is given below. 

library ieee;
use ieee.std_logic_1164.all;

entity gray_counter_tst is

end gray_counter_tst;


architecture beh of gray_counter_tst is

component gray_counter is
port(clk: in std_logic;
  rst: in std_logic;
  gray_code: out std_logic_vector (3 downto 0));
end component;
 
signal rst_s : std_logic;
signal gray_code_s : std_logic_vector(3 downto 0);
signal clk_s : std_logic := '0';          -- clk signal
constant clk_period : time := 10 ns;
begin  -- arch

DUT : gray_counter port map (
  rst => rst_s,
  clk   => clk_s,
  gray_code => gray_code_s);


process
begin  -- process clockk
    clk_s <= not clk_s;
    wait for clk_period/2;
end process;

process
begin 
 rst_s <= '1';
 wait for 11 ns;
 
 rst_s <= '0';
 wait for 200 ns;
end process;

end beh;

Test Bench is simulated using Xilinx Vivado and waveform for this simulation is given below.

Waveform of Gray Counter