Design 4-bit Linear Feedback Shift Register (LFSR) using VHDL Coding and Verify with Test Bench

Linear Feedback Shift Register is a sequential shift register with combinational feedback logic around it that causes it to pseudo randomly cycle through a sequence of binary values. Feedback around LFSR's shift register comes from a selection of points in the register chain and constitute either XORing or XNORing these points to provide point back into the register. The LFSR basically loops through repetitive sequences of pseudo random values. The maximum length of sequence is (2^n) - 1. It is used for State Encoding. It is also used to generate random numbers. Find out Verilog code here.

Design Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lfsr is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           outp : out STD_LOGIC_VECTOR (3 downto 0));
end lfsr;

architecture Behavioral of lfsr is
signal feedback : std_logic;
signal out_reg : std_logic_vector(3 downto 0):="0000";
begin
feedback <= not (out_reg(3) xor out_reg(2));
process (clk,rst)
begin
    if (rst='1') then
        out_reg <= "0000";
    elsif (rising_edge(clk)) then
        out_reg <= out_reg(2 downto 0) & feedback;
    end if;
end process;
outp <= out_reg;

end Behavioral;

Above design code is synthesized by Xilinx Vivado and RTL view of design is shown below.

RTL view of LFSR

Test Bench code for above design is given below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lfsr_tb is
--  Port ( );
end lfsr_tb;

architecture Behavioral of lfsr_tb is
signal clk_tb : std_logic := '1';
signal rst_tb : std_logic;
signal outp_tb : std_logic_vector(3 downto 0);
constant clk_period : time := 10 ns;

component lfsr is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           outp : out STD_LOGIC_VECTOR (3 downto 0));
end component;

begin
process
begin
    clk_tb <= not clk_tb;
    wait for clk_period/2;
end process;

process
begin
    rst_tb <= '1';
    wait for 6 ns;
    
    rst_tb <= '0';
    wait for 200 ns;
end process;

DUT : lfsr port map (clk_tb,rst_tb,outp_tb);

end Behavioral;

Waveform for given Test Bench is shown below.

Waveform of LFSR for given Test Bench