Design Johnson Counter and Test with Test Bench using VHDL Code

Johnson Counter is one kind of Ring Counter. It is also known as Twisted Ring Counter. A 4-bit Johnson Counter passes blocks of four logic "0" and then passes four logic "1". So it will produce 8-bit pattern. For example, "1000" is initial output then it will generate 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this patterns will repeat so on. Find out Verilog Code here.

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

library ieee;
use ieee.std_logic_1164.all;

entity johnson_counter is
port(clk : in std_logic;
  rst : in std_logic;
  op : out std_logic_vector(3 downto 0));
end entity;

architecture beh of johnson_counter is
signal opt : std_logic_vector(3 downto 0);
begin
 process (clk,rst)
  begin
   if (rst = '1') then
    opt <= "0000";
   elsif (rising_edge(clk)) then
    opt <= (not opt(0)) & opt(3 downto 1);
   end if;
  end process;
  op <= opt;
end beh;

Above design code is synthesized by Xilinx Vivado. RTL view of design is given below.

RTL view of Johnson Counter

Test bench of above design code is given below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity johnson_counter_tb is

end johnson_counter_tb;

architecture Behavioral of johnson_counter_tb is

component johnson_counter is
port(clk : in std_logic;
  rst : in std_logic;
  op : out std_logic_vector(3 downto 0));
end component;

signal clk_tb, rst_tb : std_logic := '1';
signal op_tb : std_logic_vector(3 downto 0);
constant clk_period : time := 10 ns;

begin

DUT : johnson_counter port map(clk_tb,rst_tb,op_tb);

clk_process : process
                begin
                    clk_tb <= not(clk_tb);
                    wait for clk_period/2;
                end process;
                
main_process : process
                begin
                    wait for 10 ns;
                    rst_tb <= '0';
                    wait for 100 ns;
                end process;
end Behavioral;

Test Bench is simulated by Xilinx Vivado and waveform is shown below.

Waveform of Johnson Counter