Design a Constant Divider using VHDL Coding.

Constant Divider circuit accepts an input of 8 bit wide and divides it by constant value 53. The divider circuit will generate two output values as remainder and quotient. As we know that the division operator is not synthesizable, so division is done by repetitive subtraction method. As an example of input is 108, the remainder is 2 and quotient is 2 while if input is 20, remainder is 20 and quotient is 0. In this design Inp is input with 8 bit long, Remi and Quo are two output signals with 6-bit and 3-bit long respectively. Here bit lengths of Remi and Quo are decided as per getting maximum value. Divider is constant which is 8 bit long and value is "00110101". Binary value of 53 is "00110101".

Design code is given below.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity Constant_Division is
Port(
Inp: IN std_logic_vector (7 downto 0);
remi: OUT std_logic_vector (5 downto 0);
Quo: OUT std_logic_vector (2 downto 0)
);
end Constant_Division;

architecture Behavioral of Constant_Division is
CONSTANT Divider : std_logic_vector (7 downto 0) := "00110101";

begin
process(inp)
variable q : std_logic_vector (2 downto 0);
variable x: std_logic_vector (7 downto 0):= "00000000";
 begin 
  x := inp;
  q := "000";
  if (x>= Divider) then 
   x := x-Divider;
   q:=q+"001";
   if (x>= Divider) then
    x := x-Divider;
    q:=q+"001";
    if (x>= Divider)then
    x := x-Divider;
    q:=q+"001";
     if (x>= Divider)then
      x := x-Divider;
      remi<= x(5 downto 0);
      Quo<=q+"001";
     else
      remi<=x(5 downto 0);
      Quo<=q;
     end if;
    else
     remi<=x(5 downto 0);
     Quo<=q;
    end if;
   else
    remi<=x(5 downto 0);
    Quo<=q;
   end if;
  else
   remi<=x(5 downto 0);
   Quo<=q;
  end if;
 end process;
 
end Behavioral;

Above design code is synthesized by Xilinx Vivado tool and RTL view is given below. After synthesizing this design, it consumes 31 LUTs.

RTL view of Constant Divider

Test Bench for above design code is given below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity constant_division_tb is
--  Port ( );
end constant_division_tb;

architecture Behavioral of constant_division_tb is

component Constant_Division is

Port(
Inp: IN std_logic_vector (7 downto 0);
remi: OUT std_logic_vector (5 downto 0);
Quo: OUT std_logic_vector (2 downto 0)
);
end component;

signal inp_tb : std_logic_vector(7 downto 0);
signal remi_tb : std_logic_vector(5 downto 0);
signal Quo_tb : std_logic_vector(2 downto 0);

begin

DUT : constant_division port map (inp_tb,remi_tb,Quo_tb);

process 
begin
 inp_tb <= "00000000";
 wait for 10ns;
 inp_tb <= "00110100";
 wait for 10ns;
 inp_tb <= "00110101";
 wait for 10ns;
 inp_tb <= "01101010";
 wait for 10ns;
 inp_tb <= "10011111";
 wait for 10ns;
 inp_tb <= "11110100";
 wait for 10ns;
 inp_tb <= "11010111";
 wait for 10ns;
 inp_tb <= "11010100";
 wait for 10ns;
 inp_tb <= "11111111";
 wait for 10ns;
 
end process;

end Behavioral;

Above Test Bench code is simulated using Xilinx Vivado and waveform is given below.

Waveform of Constant Divider for given Test Bench code