All About Operators in Verilog

Every language has its own set of Operators. VHDL has its own operators, same way Verilog has own set of operators to perform several operation on inputs. If you have knowledge of operators in C or C++, then it is very easy to understand operators in Verilog. There are total ten types of operators in Verilog. Operators are depending on number of operands.

• Arithmetic
• Relational
• Equality
• Logical
• Bit-wise
• Reduction
• Shift
• Concatenation
• Replication
• Conditional

• Arithmetic Operator : +(Addition), -(Subtraction), *(Multiplication), /(Division), %(Modulus), **(Exponent) are grouped under this operator category. If any operand has 'x' or 'z' value, the result of entire expression will be 'x'. The result of modulus(%) operation only takes sign of first operand.
• If A = 4'b0010; B = 1'b1101; C = 4'b1x01 //Vector of wire or reg type
• D = 3; E = 5; //Integer Type
• S = A + B; // S = 4'b1111
• S = A - B; // S = 4'b1011
• S = B - A; // S = 4'b0101
• S = A * B; // S = 4'B1111
• S = D + E; // S = 8
• S = E / D; // S = 1
• S = E ** D; // S = 125
• S = E % D; S = 1
• S = A + C; // S = 4'bx
• Relational Operator : <(Less Than), <=(Less Than or Equal to), >(Greater Than), >=(Greater Than or Equal to) are grouped under this operator category. These compare two operands and return a single bit 1, 0 or 'x' value.
• reg [3:0] a,b; a = 4'b1101; b = 4'b0110;
• a < b; //false
• a > 8; // true
• a <= b; //false
• a >= 10; // true
• a < 4'b1zzz; //unknown - x
• a < 4'b1x01; //unknown - x
• Equality Operators:
• Logical Equality : It returns 1, 0 or x value. ==(Equal to), !=(Not Equal to) are two logical equality operators.
• Case Equality: It returns only 1 or 0 value. ===(Equal to) and !==(Not Equal to) are two case equality operators.
• reg [3:0] a, b; a = 4‘b1110; b = 4'b101x;
• a ==4'b1110 // true
• a !=4'b1110 // false
• a ==4'b1z10 // false
• a != 4'b100x // true
• b == 4'b101x // unknown
• b !=4'b101x // unknown
• b === 4‘b101x // true
• b!==4'b101x // false
• Logical Operators : !(Logica| NOT or negationa), &&(Logical AND}, ||(Logical OR) are used as Logical Operators in Verilog. These return a single bit '0' or '1'. These operators are typically used in conditional statements because they work with expressions. If any operand bit is 'x' or 'z', it is equivalent to 'x' and is normally treated by the simulator as a false condition.
• reg [3:0] a, b,z; a = 4'b1100; b = 4'b00O0;
• if (a && b) z =4‘b1,'
  else z = 4'b0:
• Bit wise Operators : ~(Bitwise NOT), &(Bitwise AND), |(Bitwise OR), ^(Bitwise XOR), ~^ or ^~(Bitwise XNOR) are grouped under Bitwise Operators. These operators do bit wise operation between two operands.
• reg [7:0] p,q; p = 8'b1010xzxz; b = 8'b10010011;
• p & q = 8'b100000xx;
• p | q = 8'b1011xx11;
• p ^ q = 8'b0011xxxx;
• p ~^ q = 8'b1100xxxx;
• ~ p = 8'b0101xxxx;
• Reduction Operator : &(Reduction AND), |(Reduction OR), ~&(Reduction NAND), ~|(Reduction NOR), ^(Reduction XOR), ~^ or ^~(Reduction XNOR) are grouped under Reduction Operator in Verilog. These operators do operation on all bits of operands and return a single bit value '0' or '1'.
• reg [3:0] a,b; reg z; a = 4'b1100; b = 4'b011x;
• z = &a; // z = 0
• z = |a; // z = 1
• z = ~&a; // z = 1
• z = ~|a; //  z = 0
• z = ^a; // z = 0
• z = ~^a; // z = 1
• z = &b; // z = x
• z = ^b; // z = x
• Shift Operators : <<(Shift Lef) and >>(Shift Right) operators are grouped under Shift Operators. These operators shift first operand by the number specified as second operand. Vacant spaces are filled with zeros.
  
  
• Concatenation Operator : {} is used as cocatenation operator in Verilog. It combines two or more operands to form a larger vector.
• reg [7:0] a,b,c,z; a = 8'b11110000; b = 8'b11010000; c = 8'b11110011;
• z = {a[1:0], b[5:3], c[7:5]}; // z = 00_010_111
• Replication Operator : It is used to replicate a group of bits n times in Verilog. {n{m}} is notation used for Replication operator. This will replicate m, n times.
• {4{4'b1100}}; //1100_1100_1100_1100
• {4{4'b1100,1'bz}}; //1100z_1100z_1100z_1100z
• Conditional Operator : ? is used as Conditional Operator. This operator has following format
• (condition) ? (result if condition is true) : (result if condition is false).
• reg mux_out; wire in1, in2, sel;
• assign mux_out = sel ? in1 : in2 // if sel = 1 --> mux_out = in1, sel = 0 --> mux_out = in2
• Find out example.