VHDL Code for Ring Counter

Ring Counter is composed of Shift Registers. The data pattern will recirculate as long as clock pulses are applied. For example, if we talk about 4-bit Ring Counter, then the data pattern will repeat every four clock pulses. If pattern is 1000, then it will generate 0100, 0010, 0001, 1000 and so on. Find out Verilog Code here.

Ring Counter

Sr. No.	Name of the Pin	Direction	Width	Description
1	Clk	Input	1	Clock Signal
2	Rst	Input	1	Reset Signal
3	Op	Output	4	Output Signal

library ieee;
use ieee.std_logic_1164.all;

entity ring_counter is
port(clk : in std_logic;
  rst : in std_logic;
  op : out std_logic_vector(3 downto 0));
end entity;

architecture beh of ring_counter is
signal opt : std_logic_vector(3 downto 0);
begin
 process (clk,rst)
  begin
   if (rst = '1') then
    opt <= "1000";
   elsif (rising_edge(clk)) then
    opt <= opt(0) & opt(3 downto 1);
   end if;
  end process;
  op <= opt;
end beh;