Excitation and Characteristic Table of SR Flip Flop

The basic SR Flip-Flop is shown below. The inputs, labeled S and R are used to SET and RESET the device, respectively. The outputs Q and Q’ are complementary. Because the Flip-Flop is unclocked, any change to the inputs will produce a change at the outputs. An invalid state occurs when both inputs are low; thus, the inputs should be kept high except when the Flip-Flop is to be set or cleared. Note that there are other implementations for a latch. Here we are showing a NAND implementation.

Basic SR Flip Flop

Similar to the unclocked SR, but must be clocked each time new input conditions are sent to the Flip-Flop. The Flip-Flop is clocked each whenever the clock pulse line is high; this is a level-triggered clock. Clocked SR Flip-Flop is shown below.

Clocked SR Flip Flop

In addition to a characteristic describing the logic states of the device, a transition table is also included. The transition table shows what the input conditions must have been for a specific state transition that just occurred. Note that the input S=R=1 causes the Flip-Flop to malfunction. This is not permitted to occur. Q represents the present state and Q+ represents the next state. Characteristic and Transition table for SR Flip-Flop is given below.

Characteristic and Transition Table of SR Flip-Flop