VHDL Code for 1-Bit Full Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_con is

  port (
    a, b, c : in  std_logic;            -- inputs
    sum, ca : out std_logic);           -- sum & carry

end full_adder_con;

architecture beh of full_adder_con is

begin  -- beh

      sum <= '0' when a = '0' and b = '0' and c ='0' else
             '1' when a = '0' and b = '0' and c ='1' else
             '1' when a = '0' and b = '1' and c ='0' else
             '0' when a = '0' and b = '1' and c ='1' else
             '1' when a = '1' and b = '0' and c ='0' else
             '0' when a = '1' and b = '0' and c ='1' else
             '0' when a = '1' and b = '1' and c ='0' else
             '1' when a = '1' and b = '1' and c ='1' else
             'X';
     ca   <= '0' when a = '0' and b = '0' and c ='0' else
             '0' when a = '0' and b = '0' and c ='1' else
             '0' when a = '0' and b = '1' and c ='0' else
             '1' when a = '0' and b = '1' and c ='1' else
             '0' when a = '1' and b = '0' and c ='0' else
             '1' when a = '1' and b = '0' and c ='1' else
             '1' when a = '1' and b = '1' and c ='0' else
             '1' when a = '1' and b = '1' and c ='1' else
             'X';

end beh;