VHDL Code for Bidirectional Bus

Here I have given a block diagram of Bidirectional Bus. This bus takes input from Data_in and gives output from Bi_Data when OE signal is high. In the same way when OE signal is low then it takes input from Bi_Data and gives output from Data_Out. Below I have mentioned input output into table.

Sr. No.	Name	Direction	Width	Remark
1	Data_in	Input	16	Input Data Signal
2	Data_out	Output	16	Output Data Signal
3	Bi_Data	Inout	16	Input and Output Data Signal
4	OE	Input	1	Output Enable Signal

library ieee;
use ieee.std_logic_1164.all;

entity bidirectional_bus is

    generic (width : natural := 15); -- Width of bus
    port (Data_In : in std_logic_vector ( width downto 0 ); -- input data
            Data_Out : out std_logic_vector ( width downto 0 ); -- Output data
            Bi_Data : inout std_logic_vector ( width downto 0 ); -- Bidirectional Data Pin
            OE : in std_logic); -- Output Enable

end bidirectional_bus;

architecture beh of bidirectional_bus is
    process(OE, Bi_Data, Data_In)
      begin
         if OE = ‘1’ then
             Bi_Data <= Data_in; Data_out <= ( others => ‘Z’ );
        else
             Data_Out <= Bi_Data; Bi_Data <= ( others => ‘Z’ );
        end If;
   end process;
end beh;