Test Bench for 1x4 DeMultiplexer in VHDL

Find out DeMultiplexer Code here.

library ieee;
use ieee.std_logic_1164.all;

entity dmux1x4_seq_tst is
  
end dmux1x4_seq_tst;
 architecture beh of dmux1x4_seq_tst is
   component dmux1x4_seq
    port (
    s  : in  std_logic_vector(1 downto 0);  -- select lines
    i : in std_logic;                       -- input
   op  : out  std_logic_vector(3 downto 0)  -- outputs
   );

end component;
    signal ip_s : std_logic;  -- signals
    signal op_s : std_logic_vector(3 downto 0);  -- output signals
    signal s_s : std_logic_vector(1 downto 0);  -- select line signals
 begin  -- beh

u1 : dmux1x4_seq port map (
  i => ip_s,
  s => s_s,
  op => op_s);

tst_p: process
   begin
      ip_s<='1';
       s_s<="00";
       wait for 100 ns;
       ip_s<='1';
       s_s<="01";
       wait for 100 ns;
       ip_s<='1';
       s_s<="10";
       wait for 100 ns;
       ip_s<='1';
       s_s<="11";
       wait for 100 ns;
    end process;

 end beh;