Easy UVM (Universal Verification Methodology) Tutorial

UVM stands for Universal Verification Methodology. It is standard methodology to verify Integrated Circuits. UVM is derived from OVM, Open Verification Methodology. UVM is developed by Accellera with the support of Aldec, Cadence, Mentor Graphics and Synopsys. UVM is based on System Verilog language. With the help of UVM, engineers are able to create an efficient verification environment. It is portable from one project to another. Due to portability, engineers can reuse testbench from previous projects and modify different components as per their need. UVM easy tutorial is shown below. It is available on YouTube. It is developed by John Aynsley from Doulos. There are twenty videos. After watching this tutorial, overall picture of UVM will be cleared. 

Introduction

UVM Part 1

UVM Part 2

UVM Part 3

Easier UVM - 1

Easier UVM - 2

Key Concepts of the Easier UVM Code Generator

UVM and EDA Playground

Phases and Components of UVM

Configuration in UVM

UVM TLM Connection

Transaction Classes in UVM

Sequences in UVM

Tests in UVM

Reporting in UVM

Register Layer in UVM

Parameterized Interface in UVM

Scoreboard in UVM

Broader View of UVM Sequences

Run Time Phasing of UVM