Test Bench for 1-Bit Full-Adder in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_con_tst is
  
end full_adder_con_tst;
 architecture beh of full_adder_con_tst is
   component full_adder_con
       port (
    a,b,c: in  std_logic;   -- inputs
    sum,ca: out std_logic);  -- outputs

end component;
    signal a_s,b_s,c_s : std_logic;  -- signals
    signal sum_s,ca_s : std_logic;  -- output signals
 begin  -- beh

u1 : full_adder_con port map (
  a => a_s,
   b => b_s,
   c => c_s,
   sum => sum_s,
  ca => ca_s);

tst_p: process
   begin
      a_s<='0';
       b_s<='0';
       c_s<='0';
       wait for 100 ns;
       a_s<='0';
       b_s<='0';
       c_s<='1';
       wait for 100 ns;
       a_s<='0';
       b_s<='1';
       c_s<='0';
       wait for 100 ns;
       a_s<='0';
       b_s<='1';
       c_s<='1';
       wait for 100 ns;
       a_s<='1';
       b_s<='0';
       c_s<='0';
       wait for 100 ns;
       a_s<='1';
       b_s<='0';
       c_s<='1';
       wait for 100 ns;
       a_s<='1';
       b_s<='1';
       c_s<='0';
       wait for 100 ns;
       a_s<='1';
       b_s<='1';
       c_s<='1';
       wait for 100 ns;
    end process;
 end beh;