Test Bench for 4x1 Multiplexer in VHDL

Find out Design code of 4x1 Mux here.

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1_seq_tst is
  
end mux4x1_seq_tst;
 architecture beh of mux4x1_seq_tst is
   component mux4x1_seq
   port (
    ip0 : in  std_logic;   -- input pin
    ip1 : in  std_logic;   -- input pin
    ip2 : in  std_logic;   -- input pin
    ip3 : in  std_logic;   -- input pin
    s : in std_logic_vector(0 to 1);     --select line
    op : out std_logic);  -- output 

end component;
    signal  ip0_s :  std_logic;   -- input signal
   signal  ip1_s :  std_logic;   -- input signal
   signal ip2_s :  std_logic;   -- input signal
   signal ip3_s :  std_logic;   -- input signal
   signal  s_s :  std_logic_vector(0 to 1);     --msb of select line signal
   signal  op_s :  std_logic;  -- output siganl
 begin  -- beh

u1 : mux4x1_seq port map (
  ip0 => ip0_s,
   ip1 => ip1_s,
   ip2 => ip2_s,
   ip3 => ip3_s,
   s => s_s,
  op => op_s);
tst_p: process
   begin
      ip0_s<='1';
       ip1_s<='0';
       ip2_s<='0';
       ip3_s<='0';
       s_s<="00";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='1';
        ip2_s<='0';
        ip3_s<='0';
       s_s<="10";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='0';
        ip2_s<='1';
        ip3_s<='0';
       s_s<="01";
       wait for 100 ns;
        ip0_s<='0';
        ip1_s<='0';
        ip2_s<='0';
        ip3_s<='1';
       s_s<="11";
       wait for 100 ns;
   end process;

 end beh;