VHDL Code for 16x9 True Dual Port Memory

Name of the Pin	Direction	Width	Description
address1	Input	4	Input address1 i.e. address bus1
address2	Input	4	Input address2 i.e. address bus2
we1	Input	1	If 0 write in to memory & if 1 read from memory
we2	Input	1	If 0 write in to memory & if 1 read from memory
data1	Input	9	input data1
data2	Input	9	input data2
data_out1	output	9	output data1
data_out2	output	9	output data2

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity dual_port_ram is

  port (
    clk            : in std_logic;      -- clk is the clock input.

    ce_l_1, ce_l_2 : in std_logic;  -- ce_l_1, ce_l_2 is the chip enable of port 1 and port 2.

    oe_l_1, oe_l_2 : in std_logic;  -- oe_l_1, oe_l_2 is active low output enable of port 1 and port 2.

    r_w_1, r_w_2   : in std_logic;  -- r_w_1, r_w_2 is read/write signal of port 1 and port 2.

    data_1, data_2 : inout std_logic_vector(8 downto 0);  -- data_1 and data_2 is the data input & output from the memory.

    addr1          : in std_logic_vector(3 downto 0);  -- addr1 is the address for port 1
    addr2          : in std_logic_vector(3 downto 0));  -- addr_2 is the address input for port 2.

end dual_port_ram;

architecture dp_ram of dual_port_ram is

  signal cntrl_1_p1, cntrl_2_p1, cntrl_1_p2, cntrl_2_p2 : std_logic;  -- cntrl_1_p1, cntrl_2_p1, cntrl_1_p2, cntrl_2_p2 are used to generate control signals for reading or writing into memory.

  type mem is array (15 downto 0) of std_logic_vector(8 downto 0);  -- mem is used to define memory.

  shared variable memory : mem;         -- memory is used to define memory.

begin  -- dp_ram

  cntrl_1_p1 <= not((not ce_l_1) and (not r_w_1)); -- control signal for read/write operation for port 1.

  cntrl_2_p1 <= not((not ce_l_1) and (not oe_l_1)); -- control signal for output enable for port 1.

  cntrl_1_p2 <= not((not ce_l_2) and (not r_w_2)); -- control signal for read/write operation for port 2.

  cntrl_2_p2 <= not((not ce_l_2) and (not oe_l_2)); -- control signal for output enable for port 2.

  ----------------------------------------------
  -- purpose: It is used to access port 1.
  -- type   : sequential
  -- inputs : clk, ce_l_1, oe_l_1, r_w_1, data_1
  -- outputs: data_1
  ----------------------------------------------
  port1: process (clk)
  begin  -- process port1
    if clk'event and clk = '1' then  -- rising clock edge
      if cntrl_1_p1 = '0' and cntrl_2_p1 = '1' then  -- Write Operation.
        memory(conv_integer(addr1)) := data_1;
      elsif cntrl_1_p1 = '1' and cntrl_2_p1 = '0' then  -- Read Operation.
        data_1 <= memory(conv_integer(addr1));
      else
        data_1 <= "ZZZZZZZZZ";
      end if;
    end if;
  end process port1;


  -------------------------------------------------------
  -- purpose: It is used to accesss port 2.
  -- type   : sequential
  -- inputs : clk, cs_l_2, oe_l_2, addr_2, data_2, r_w_2
  -- outputs: data_2
  -------------------------------------------------------
  port2: process (clk)
  begin  -- process port2
    if clk'event and clk = '1' then  -- rising clock edge
      if cntrl_1_p2 = '0' and cntrl_2_p2 = '1' then  -- Write Operation.
        memory(conv_integer(addr2)) := data_2;
      elsif cntrl_1_p2 = '1' and cntrl_2_p2 = '0' then  -- Read Operation.
        data_2 <= memory(conv_integer(addr2));
      else
        data_2 <= "ZZZZZZZZZ";
      end if;
    end if;
  end process port2;

end dp_ram

VHDL Code for 16x9 Memory

Sr. No.	Name of the Pin	Direction	Width	Description
1	addr	Input	4	Input address i.e. address bus
2	oe	input	1	output enable
3	wr_l	Input	1	If 0 write in to memory & if 1 read from memory
4	data	Input/Output	9	Output read/write from/to memory i.e. bidirectional data bus MSB is parity bit

Memory Code

library IEEE;
use IEEE.std_logic_1164.all;

entity memory is
 port (data : inout std_logic_vector (8 downto 0);  -- databus
         
   addr : in std_logic_vector (3 downto 0);     -- address bus
         
  oe, wr_l, clk : in std_logic);             -- control signals

end entity;

architecture arch  of memory is

  ----------------------------------------
  -- Instantiation of D flipflop component
  ----------------------------------------
  component d_ff is
    port (d_in , en , clk : in std_logic;
          q : out std_logic);
  end component;

  -------------------------------------
  -- Instantiation of Decoder component
  -------------------------------------
  component decoder_4x16 is

    port (
      i : in  std_logic_vector (3 downto 0);   -- input ports
      o : out std_logic_vector (15 downto 0));  -- output ports

  end component;

  -----------------------------------
  -- Instantiation of Tristate buffer
  -----------------------------------
  component tri_state is

    port (
      en    : in  std_logic;
      d_in  : in  std_logic_vector (8 downto 0);
      d_out : out std_logic_vector (8 downto 0));

  end component;
-------------------------------
-- function to calculate parity
-------------------------------
   function parity_gen_func (par : in std_logic_vector (7 downto 0)) return std_logic is
  begin

  return par(0)xor par(1)xor par(2)xor par(3)xor par(4)xor par(5)xor par(6)xor par(7);

  end parity_gen_func;

 
  type temp is array ( 15 downto 0) of std_logic_vector (8 downto 0);

  signal row : std_logic_vector (15 downto 0);  -- temporary row address container

  signal d_ff_out : temp;               -- temporary data

  signal en_tri_state : std_logic_vector (15 downto 0);  --enable signal for
                                                         --tristate buffer

begin  -- arch

  --------------------------
  -- Memory address decoding
  --------------------------
  dec: decoder_4x16 port map (i => addr,
                             o => row);

  -----------------------------------------------
  --Selecting flipflop for row and column address
  -----------------------------------------------
 
  generate_dff_coloumn:  for i in 7 downto 0 generate
    generate_dff_row: For j in 15 downto 0 generate
    dff: d_ff port map (
      d_in => data(i),
      en => row(j),
      clk => clk,
      q => d_ff_out(j)(i));
  end generate generate_dff_row;
end generate generate_dff_coloumn;

  generate_row_8 :  for i in 15 downto 0 generate
    assert data(8)=parity_gen_func(data(7 downto 0)) report "parity error" severity error;
    dff1 : d_ff port map (
                              d_in => data(8),
                              en => row(i),
                              clk => clk,
                              q => d_ff_out(i)(8));
      end generate generate_row_8;


    --------------------------------------------------------
    --Tristate buffer for input/output operation for data bus
    --------------------------------------------------------
    generate_tri_state: for i in 15 downto 0 generate
      tri_state_buffer: tri_state port map (
        en => en_tri_state(i),
        d_in => d_ff_out(i),
        d_out => data);
    end generate generate_tri_state;

    -----------------------------------
    --Enable signal for tristate buffer
    -----------------------------------
    process(row,wr_l,oe)
    begin
      for i in 15 downto 0 loop
        en_tri_state(i) <= ((oe and wr_l) and (row(i)));
    end loop;
 
    end process;
 
end arch ;

D_ff Code

library IEEE;
use IEEE.std_logic_1164.all;

entity d_ff is
port (d_in , en , clk : in std_logic;
 q : out std_logic);
end entity;

architecture arch of d_ff is
begin
  process(clk,en,d_in)
    begin
    if (en='1') then
      if (clk'event and clk='1') then 
        q <= d_in;
      end if;
    end if;
  end process;
end arch;

Decoder_4x16 Code

library ieee;
use ieee.std_logic_1164.all;

entity decoder_4x16 is
  
  port (
    i : in  std_logic_vector (3 downto 0);   -- input ports
    o : out std_logic_vector (15 downto 0));  -- output ports

end decoder_4x16;

architecture arch of decoder_4x16 is

begin  -- deoder_concr_arch

  with i select
    o <=
    "0000000000000001" when "0000",
    "0000000000000010" when "0001",
    "0000000000000100" when "0010",
    "0000000000001000" when "0011",
    "0000000000010000" when "0100",
    "0000000000100000" when "0101",
    "0000000001000000" when "0110",
    "0000000010000000" when "0111",
    "0000000100000000" when "1000",
    "0000001000000000" when "1001",
    "0000010000000000" when "1010",
    "0000100000000000" when "1011",
    "0001000000000000" when "1100",
    "0010000000000000" when "1101",
    "0100000000000000" when "1110",
    "1000000000000000" when "1111",
    "XXXXXXXXXXXXXXXX" when others;

end arch;

Tri-state Code

library IEEE;
use IEEE.std_logic_1164.all;

entity tri_state is
  
  port (
    en    : in  std_logic;
    d_in  : in  std_logic_vector (8 downto 0);
    d_out : out std_logic_vector (8 downto 0));

end tri_state;

architecture arch of tri_state is

begin  -- arch

    with en select
    d_out <=
    d_in when '1',
    "ZZZZZZZZZ" when '0',
    "XXXXXXXXX" when others;

end arch;

VHDL Code for 8-bit Barrel Shifter

Sr. No.	Name of the Pin	Direction	Width	Description
1	d_in	Input	8	data input
2	Shift_by	Input	3	shift amount
3	Rst_a	Input	1	Reset signal
4	Clk	Input	1	Clock signal
5	Shift_lt_rt	Input	1	‘0’=shift left ‘1’=shift right
6	P_load	Input	1	‘1’=receive input data ‘0’=discard input data
7	D_out	Output	8	Parallel data output

Barrel shifter takes parallel data input and give shifted output either in left or right direction by a specific shift amount. When shift_by input is “000” it will place input data at the output without shifting. For specifying shifting direction shift_lt_rt pin is used. When it is ‘0’ the block will perform left shift operation and when it is ‘1’, it will perform right operation. Find out Test Bench here.

VHDL Code for Parity Generator using Function

When valid_in is ‘1’ it will accept serial input and that serial input goes for parallel output. After receiving eight bit of serial input this block converts the serial input to parallel output. Valid_out signal goes ‘1’ after receiving eight bytes of serial data & gives parallel data on the data_o. After valid_out goes high parity_out signal gives parity of the input data. Valid_out signal goes high on each eighth clock cycle & remain high for one cycle.

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
entity parity_generator is 

  port( clk       :in std_logic;    --clock signal
        d_in      :in std_logic;    --serial data input
        valid_in  :in std_logic;    --valid input signal
        rst_a     :in  std_logic;   --reset signal
        valid_out :out std_logic;   --valid output signal
        parity_out:out std_logic;   --parity check signal
        data_o        :out std_logic_vector(7 downto 0)); --parallel data output
       
end parity_generator; 


architecture archi of parity_generator is

--fuction to check parity of output data
function parity_chk (constant i : std_logic_vector(7 downto 0)) 
    return std_logic is 
    begin
    return (i(0) xor i(1) xor i(2) xor i(3) xor i(4) xor i(5) xor i(6) xor i(7));
end parity_chk;

 subtype cnt8 is integer range 0 to 8; 

 
    --signal tmp: std_logic_vector(7 downto 0) := "00000000";
    --signal cnt : cnt8 := 0; -- counter to count 8 serial input data.
  begin 
process (clk,rst_a)
  variable tmp: std_logic_vector(7 downto 0);
  variable cnt: cnt8 := 0;
  begin  
    if (rst_a = '1') then
      data_o<="00000000";
      valid_out<='0';
      parity_out<='-';
    elsif (clk'event and clk='1') then
      if(valid_in='1') then
        tmp:=tmp(6 downto 0)& d_in;
        cnt:=cnt+1;
      if(cnt = 8) then
        valid_out<='1';
        data_o<=tmp;
        parity_out <= parity_chk(tmp);
        cnt:=0;
      else 
        valid_out <= '0';
        parity_out <= '-';
        data_o<="XXXXXXXX";  
      end if;
    end if;
  end if;
end process;
end archi; 

VHDL Code for 4-bit Up-Down Counter with Pre-Load

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity up_counter_sync_preload is
  
  port(clk, rst_a,load : in std_logic; 
       ip: in std_logic_vector(3 downto 0);
        q : out std_logic_vector(3 downto 0)); 

end up_counter_sync_preload; 

architecture archi of up_counter_sync_preload is 

   begin  
    process (clk, rst_a)
      variable tmp,cnt : std_logic_vector(3 downto 0):="0000";
      begin 
        if (rst_a='1') then 
          tmp := "0000"; 
       elsif (clk'event and clk='1') then
          cnt:=tmp; 
          if (load='1') then
          tmp := ip;
           else 
          tmp := tmp + '1';
          end if;
          assert (tmp-cnt="0001") report "count differ by 1 violate" severity warning;
      end if;
          q<=tmp;
    end process;
    

end archi;

VHDL Code for 4-bit Up-Down Counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity up_down_counter is

  port(clk, rst_a, mode : in std_logic;  --mode=1 up counting, mode=0 down counting
        q : out std_logic_vector(3 downto 0));

end up_down_counter;

architecture archi of up_down_counter is
  signal tmp: std_logic_vector(3 downto 0);
  begin
    process (clk, rst_a)
      begin
        if (rst_a='1') then
          tmp <= "0000";
        elsif (clk'event and clk='1') then
          if (mode='1') then
            tmp <= tmp + 1;
          else
            tmp <= tmp - 1;
          end if;
        end if;
    end process;
    q <= tmp;
end archi;

VHDL Code for Asynchronous Reset D-FlipFlop

library ieee;
use ieee.std_logic_1164.all;

  entity dff_async_reset is
      port (
          data    :in  std_logic;  -- Data input
          clk     :in  std_logic;  -- Clock input
          reset_a :in  std_logic;  -- Reset input
          q       :out std_logic;  -- Q output
          enb     :in  std_logic;  -- enable pin
          load    :in  std_logic   -- load the input
      );
  end entity;

  architecture beh of dff_async_reset is

  begin
      process (clk,reset_a,enb,load)
           begin
         
          if (reset_a = '1') then
              q <= '0';
          elsif(rising_edge(clk) and enb ='1') then
              if(load = '1') then
                q <= '1';
              else
                q<= data;
              end if;          
          end if;
    end process;
end architecture;

VHDL Code for 4-Bit Magnitude Comparator

Given below code is about 4-bit Magnitude comparator. First code is written using structural method and second code is written using behavioral method. This module has two 4-bit inputs 'a' and 'b' and three single bit output 'ag', bg' and 'eq'. In this code if 'a' is greater than 'b' then 'ag' will go high and rest will be low. Same way if 'b' is grater than 'a' then 'bg' will go high and rest will go low. If 'a' and 'b' are equal then 'eq' will go high and rest will go low. Find out Test Bench here.

VHDL Code for Half-Adder

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is

  port (
    ip1 : in  std_logic;
    ip2 : in  std_logic;
    sum : out std_logic;
    ca  : out std_logic);

end half_adder;

architecture half_adder_beh of half_adder is

begin  -- half_adder_beh

  sum <= ip1 xor ip2;
  ca <= ip1 and ip2;

end half_adder_beh;

VHDL Code for 4-bit Full-Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_4b is

  port (
    a,b : in std_logic_vector(3 downto 0);
    s : out std_logic_vector(3 downto 0);
    c : inout std_logic_vector(4 downto 1)
    );
 
end full_adder_4b;

architecture beh of full_adder_4b is
constant c0 : std_logic := '0';         -- carry to the first full adder block
begin  -- beh

  s(0) <= a(0) xor b(0) xor c0;
  c(1) <= (a(0) and b(0))or(b(0) and c0)or(a(0) and c0);
  s(1) <= a(1) xor b(1) xor c(1);
  c(2) <= (a(1) and b(1))or(b(1) and c(1))or(a(1) and c(1));
  s(2) <= a(2) xor b(2) xor c(2);
  c(3) <= (a(2) and b(2))or(b(2) and c(2))or(a(2) and c(2));
  s(3) <= a(3) xor b(3) xor c(3);
  c(4) <= (a(3) and b(3))or(b(3) and c(3))or(a(3) and c(3));

end beh;

VHDL Code for Round Robin Arbiter with Variable Time Slice

Round Robin Arbiter will grant the request on circular basis. In this design code, there are four requests and four grant signals. This code will grant the request to first, second third and forth at the last. This code will grant the user request for four clock cycle and this time slice can be varied. This code can be modified for different time slices according to specification. Find Round Robin Arbiter with fixed time slice here.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity round_robin1 is
 
  port (
    clk   : in  std_logic;                      -- clock signal
    rst   : in  std_logic;                      -- reset signal
    req   : in  std_logic_vector(3 downto 0);   -- request vector
    grant : out std_logic_vector(3 downto 0));  -- grant vector

end round_robin1;

architecture beh of round_robin1 is

  type state is (s_ideal,s0,s1,s2,s3);          -- 4 states for 4 request users
  signal p_state : state := s_ideal;         -- present state
  signal count : std_logic_vector(1 downto 0) := "00";  -- counter for time
 

begin  -- beh

main: process (clk,rst,count)
begin  -- process main
  if rst='1' then
    count<="00";
    p_state<=s_ideal;
    grant<="0000";
  elsif rising_edge(clk) then
    case p_state is

      when s0 =>
        if req(0)='1' then
          if count="11" then
            if req(1)='1' then
              count<="00";
              p_state<=s1;
            elsif req(2)='1' then
              count<="00";
              p_state<=s2;
            elsif req(3)='1' then
              count<="00";
              p_state<=s3;
            else
              count<="00";
              p_state<=s0;
            end if;
          else
            count<=count+'1';
            grant<="0001";
            p_state<=s0;
          end if;
        elsif req(1)='1' then
          p_state<=s1;
          count<="00";
        elsif req(2)='1' then
          p_state<=s2;
          count<="00";
        elsif req(3)='1' then
          p_state<=s3;
          count<="00";
        else
          p_state<=s_ideal;
      end if;

      when s1 =>
      if req(1)='1' then
        if count="11" then
          if req(2)='1' then
            count<="00";
            p_state<=s2;
          elsif req(3)='1' then
            count<="00";
            p_state<=s3;
          elsif req(0)='1' then
            count<="00";
            p_state<=s0;
          else
            count<="00";
            p_state<=s1;
          end if;
        else
          count<=count+'1';
          grant<="0010";
          p_state<=s1;
        end if;
      elsif req(2)='1' then
        p_state<=s2;
        count<="00";
      elsif req(3)='1' then
        p_state<=s3;
        count<="00";
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

      when s2 =>
      if req(2)='1' then
        if count="11" then
          if req(3)='1' then
            count<="00";
            p_state<=s3;
          elsif req(0)='1' then
            count<="00";
            p_state<=s0;
          elsif req(1)='1' then
            count<="00";
            p_state<=s1;
          else
            count<="00";
            p_state<=s2;
          end if;
        else
          count<=count+'1';
          grant<="0100";
          p_state<=s2;
        end if;
      elsif req(3)='1' then
        p_state<=s3;
        count<="00";
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      elsif req(1)='1' then
        p_state<=s1;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

      when s3 =>

      if req(3)='1' then
        if count="11" then
          if req(0)='1' then
            count<="00";
            p_state<=s0;
          elsif req(1)='1' then
            count<="00";
            p_state<=s1;
          elsif req(2)='1' then
            count<="00";
            p_state<=s2;
          else
            count<="00";
            p_state<=s3;
          end if;
        else
          count<=count+'1';
          grant<="1000";
          p_state<=s3;
        end if;
      elsif req(0)='1' then
        p_state<=s0;
        count<="00";
      elsif req(1)='1' then
        p_state<=s1;
        count<="00";
      elsif req(2)='1' then
        p_state<=s2;
        count<="00";
      else
        p_state<=s_ideal;
      end if;

     
      when others =>
        if req(0)='1' then
          p_state<=s0;
          count<="00";
        elsif req(1)='1' then
          p_state<=s1;
          count<="00";
        elsif req(2)='1' then
          p_state<=s2;
          count<="00";
        elsif req(3)='1' then
          p_state<=s3;
          count<="00";
        else
            p_state<=s_ideal;
            count<="00";
            grant<="0000";
        end if;
    end case;
  end if;
end process main;

end beh;

VHDL Code for 1-Bit Full Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_adder_con is

  port (
    a, b, c : in  std_logic;            -- inputs
    sum, ca : out std_logic);           -- sum & carry

end full_adder_con;

architecture beh of full_adder_con is

begin  -- beh

      sum <= '0' when a = '0' and b = '0' and c ='0' else
             '1' when a = '0' and b = '0' and c ='1' else
             '1' when a = '0' and b = '1' and c ='0' else
             '0' when a = '0' and b = '1' and c ='1' else
             '1' when a = '1' and b = '0' and c ='0' else
             '0' when a = '1' and b = '0' and c ='1' else
             '0' when a = '1' and b = '1' and c ='0' else
             '1' when a = '1' and b = '1' and c ='1' else
             'X';
     ca   <= '0' when a = '0' and b = '0' and c ='0' else
             '0' when a = '0' and b = '0' and c ='1' else
             '0' when a = '0' and b = '1' and c ='0' else
             '1' when a = '0' and b = '1' and c ='1' else
             '0' when a = '1' and b = '0' and c ='0' else
             '1' when a = '1' and b = '0' and c ='1' else
             '1' when a = '1' and b = '1' and c ='0' else
             '1' when a = '1' and b = '1' and c ='1' else
             'X';

end beh;

VHDL Code for 4x1 Multiplexer

Find out Test Bench for 4x1 Mux here.

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1_seq is
  
port (
  ip0, ip1, ip2, ip3 : in  std_logic;
  s                  : in  std_logic_vector(0 to 1);
  op                 : out std_logic);
end mux4x1_seq;

architecture beh of mux4x1_seq is

begin  -- beh
p_mux : process (ip0,ip1,ip2,ip3,s)
  variable temp : std_logic;
  begin
    case s is
      when "00" => temp := ip0 ;
      when "01" => temp := ip1;
      when "10" => temp := ip2;
      when others => temp := ip3;
    end case;
    op <= temp;
  end process p_mux;

end beh;

VHDL Code for 1x4 DeMultiplexer

Function of DeMultiplexer is opposite of Multiplexer. It has one input and several output based on control signal. Find out Test Bench here.

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library ieee;
use ieee.std_logic_1164.all;

entity dmux1x4_seq is
  
  port (
    i : in  std_logic;                      -- input lines
    s : in  std_logic_vector(1 downto 0);   -- select lines
    op : out std_logic_vector(3 downto 0));

end dmux1x4_seq;

architecture beh of dmux1x4_seq is
  
begin  -- beh

u1 : process (i,s)
 variable temp : std_logic_vector(0 to 3);
  begin  -- process u1
    case s is
      when "00" => temp := "000"&i;
      when "01" => temp := "00"&i&'0';
      when "10" => temp := '0'&i&"00";
      when "11" => temp := i&"000";
      when others => null;
    end case;
    op <= temp;
  end process u1;
end beh;

VHDL Code for 8x3 Encoder

Encoder is a combinational circuit which converts set of signal into equivalent code. Function is exactly opposite of Decoder. Find out Test Bench for 8x3 Encoder here.

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library ieee;
use ieee.std_logic_1164.all;


entity enco8x3_seq is
  
  port (
    i : in  std_logic_vector(7 downto 0);  -- inputs
    o : out std_logic_vector(2 downto 0));  -- outputs

end enco8x3_seq;


architecture beh of enco8x3_seq is

begin  -- beh

  enco : process (i)
  variable temp : std_logic_vector(2 downto 0);
  begin
    case i is
      when "00000001" => temp := "000";
      when "00000010" => temp := "001";
      when "00000100" => temp := "010";
      when "00001000" => temp := "011" ;
      when "00010000" => temp := "100";
      when "00100000" => temp := "101";
      when "01000000" => temp := "110";
      when "10000000" => temp := "111";
      when others => temp := "XXX";
    end case;
    o <= temp;
  end process enco;

end beh;